--report thermal`
An example of the output is shown below
```
-------------------------------------------------
[0000:3b:00.1] : xilinx_u55c_gen3x16_xdma_base_3
-------------------------------------------------
Thermals
Temperature : Celcius
PCB Top Front : 36 C
PCB Top Rear : 32 C
FPGA : 38 C
Int Vcc : 41 C
```
- - -
### Use system logs to see if the card exceeded power or thermal limits
XRT will log if there has been a critical event in `dmesg` similar to below:
```
[93352.134536] xclmgmt 0000:a3:00.0: clock.m.25165825 ffff90a92b74a010 clock_status_check: Critical temperature or power event, kernel clocks have been stopped.
[93352.134643] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: AXI Firewall 3 tripped, status: 0x80004, bar offset 0x3000, resource ep_firewall_ctrl_user_00 1 0 1 axi_firewall
[93352.134648] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 0, ep ep_firewall_blp_ctrl_mgmt_00 1 0 1 axi_firewall, status: 0x0, bar offset 0x1f02000
[93352.134652] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 1, ep ep_firewall_blp_ctrl_user_00 1 0 1 axi_firewall, status: 0x0, bar offset 0x1f03000
[93352.134657] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 2, ep ep_firewall_ctrl_mgmt_00 1 0 1 axi_firewall, status: 0x0, bar offset 0x2000
[93352.134661] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 3, ep ep_firewall_ctrl_user_00 1 0 1 axi_firewall, status: 0x80004, bar offset 0x3000
[93352.134666] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 4, ep ep_firewall_ctrl_debug_00 1 0 1 axi_firewall, status: 0x0, bar offset 0x4000
[93352.134670] xclmgmt 0000:a3:00.0: firewall.m.12582914 ffff90a92e634c10 check_firewall: Firewall 5, ep ep_firewall_data_h2c_00 1 0 1 axi_firewall, status: 0x0, bar offset 0x5000
[93352.134672] xclmgmt 0000:a3:00.0: health_check_cb: Card requires pci hot reset
```
There will be no mention if this is a temperature or power event.
There may be an indication of an over temperature event earlier in `dmesg` as XRT will log if a device is approaching the temperature limits as below:
````
[686835.888454] xclmgmt 0000:05:00.0: check_temp_within_range: Warning: A Xilinx acceleration device is reporting a temperature of 96C. There is a card shutdown limit if the device hits 97C. Please keep the device below 88C.
[686836.200333] xocl 0000:05:00.1: ffff8a0e1e23f098 _xocl_drvinst_open: OPEN 2
````
If the limits are exceeded in either case, the device will be shut down. Often a firewall trip can be observed as below:
```
[67066.484066] firewall.m firewall.m.10485760: dev ffff9b24390edc10, check_firewall: AXI Firewall 3 tripped, status: 0x4, bar offset 0x3000, resource ep_firewall_ctrl_user_00 1 0 1
[67066.484070] xclmgmt 0000:03:00.0: health_check_cb: Card is in a Bad state, notify userpf
```
This indicates the device was shutdown to protect it.
You can also expect to see a firewall trip message in [xbutil examine](https://xilinx.github.io/XRT/master/html/xbutil.html#xbutil-examine) as shown below:
```
Card Power(W)
16
~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
Firewall Last Error Status
Level 3 : 0x80004(RECS_CONTINUOUS_RTRANSFERS_MAX_WAIT|RECS_WRITE_TO_BVALID_MAX_WAIT)
Error occurred on: Wed 2020-08-19 13:59:13 MDT
```
To actively monitor the card's power and temperature during runtime, use the script provided in the [monitoring power and temperature](common-steps.html#monitor-card-power-and-temperature) section.
- - -
### Reverting the card to factory image
Xilinx Alveo cards might need to be reverted to their factory (or golden) image. This is recommended when:
* Preparing to flash a different shell onto the card
* Preparing to upgrade or change the version of XRT installed on the host
* The card no longer appears on lspci after programming a custom image onto the card
[AR71757 Reverting Card to Factory image](https://www.xilinx.com/support/answers/71757.html) provides methods to revert the card using either the Vitis/XRT or Vivado flow.
- - -
### Vivado HW Manager
***This is for the more advanced user comfortable with manually programming FPGAs***
If a card can't be seen by multiple systems via `lspci`, the next step is to see if the FPGA is alive by determining if it can be seen in Vivado HW manager. The steps for connecting the U50/U55C and U200/250/280 cards are below.
For the U50 and U55C:
1. An Alveo Programming Cable is necessary to see the U50/U55C in Vivado Hardware Manager
2. The Alveo Programming Cable is shown in Figure 3 in UG1377: [UG1377 V1.1](https://www.xilinx.com/support/documentation/boards_and_kits/accelerator-cards/ug1377-alveo-programming-cable-user-guide.pdf)
3. Follow the directions in UG1377 to connect the Alveo Programming Cable between a computer and the card.
a. Pages 1-13
b. Often the debug machine is a windows laptop
4. Open Vivado hardware manager
5. Tools → Auto connect
6. `set_property PARAM.FREQUENCY 1000000 [current_hw_target]`
7. The FPGA should be displayed. In the following example the xu50\_0 is displayed:
![HW Manager](./images/initial_connection.png)
8. If the device shows up in Vivado HW Manager follow [AR 71757](https://www.xilinx.com/support/answers/71757.html) to revert the card back to the golden image
9. Otherwise the FPGA is not working, post on the
[Xilinx forums](https://support.xilinx.com/s/topic/0TO2E000000YKXlWAO/alveo-accelerator-cards)
For the U200/U250/U280:
1. Plug in JTAG cable between U200/U250/U280 card and debug machine
a. Often the debug machine is a windows laptop
2. Open Vivado hardware manager
3. Tools → Auto connect
4. `set_property PARAM.FREQUENCY 1000000 [current_hw_target]`
5. The xcu200\_0 should show as below:
![HW Manager](./images/initial_connection_u2xx.PNG)
6. If the device shows up in Vivado HW Manager follow [AR 71757](https://www.xilinx.com/support/answers/71757.html) to revert the card back to the golden image
7. Otherwise the FPGA is not working, post on the
[Xilinx forums]https://support.xilinx.com/s/topic/0TO2E000000YKXlWAO/alveo-accelerator-cards)
- - -
### Xilinx Support
For additional support resources such as Answers, Documentation, Downloads, and Alerts, see the [Xilinx Support pages](http://www.xilinx.com/support). For additional assistance, post your question on the Xilinx Community Forums – [Alveo Accelerator Card](https://support.xilinx.com/s/topic/0TO2E000000YKXlWAO/alveo-accelerator-cards).
Have a suggestion, or found an issue please send an email to alveo_cards_debugging@xilinx.com .
### License
All software including scripts in this distribution are licensed under the Apache License, Version 2.0 (the "License"); you may not use this file except in compliance with the License.
You may obtain a copy of the License at
[http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0)
All images and documentation, including all debug and support documentation, are licensed under the Creative Commons (CC) Attribution 4.0 International License (the "CC-BY-4.0 License"); you may not use this file except in compliance with the CC-BY-4.0 License.
You may obtain a copy of the CC-BY-4.0 License at
[https://creativecommons.org/licenses/by/4.0/]( https://creativecommons.org/licenses/by/4.0/)
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.
XD027 | © Copyright 2021 Xilinx, Inc.