This document provides an introduction to using the Xilinx® Vivado® Design Suite flow for using the Zynq®-7000 SoC device. The examples are targeted for the Xilinx ZC702 Rev 1.0 evaluation board and the tools used are the Vivado® Design Suite and the Vitis™ unified software platform.

The examples in this document were created using the Xilinx tools running on Windows 7, 64-bit operating system, and PetaLinux on Linux 64-bit operating system. Other versions of the tools running on other Window installs might provide varied results. These examples focus on introducing you to the following aspects of embedded design.

  1. Introduction

  2. Using the Zynq SoC Processing System

  3. Debugging with the Vitis Software Platform

  4. Building and Debugging Linux Applications for Zynq-7000 SoCs

  5. Using the GP Port in Zynq Devices

  6. Using the HP Slave Port with AXI CDMA IP

  7. Linux Boot Image Configuration

  8. Creating Custom IP and Device Drivers for Linux

Example Project

The best way to learn a tool is to use it. So, this guide provides opportunities for you to work with the tools under discussion. Specifications for sample projects are given in the example sections, along with an explanation of what is happening behind the scenes. Each chapter and examples is intended to showcase different aspects of embedded design. The example takes you through the entire flow to complete the learning and then moves on to another topic.

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