2020.1 Vitis™ Application Acceleration Tutorials

See 2019.2 Vitis Application Acceleration Development Flow Tutorials

Vitis HLS Analysis and Optimization


Vitis High-Level Synthesis (HLS) is a key part of the Vitis application acceleration development flow. The tool is responsible for compiling C/C++ and OpenCL code into a kernel for acceleration in the programmable logic (PL) region of Xilinx devices. Thus, it is the tool that compiles the hardware kernels for the Vitis tools by performing high-level synthesis.

In this tutorial, you will work through the Vitis HLS tool GUI to build, analyze, and optimize a hardware kernel. You are working through the Vitis kernel flow in the Vitis tool. For more information, refer to Enabling the Vitis Kernel Flow in the Vitis HLS Flow of the Vitis Unified Software Platform Documentation (UG1416).

Before You Begin

The labs in this tutorial use:

  • BASH Linux shell commands.

  • 2020.1 Vitis core development kit release and the xilinx_u200_xdma_201830_2 platform. If necessary, it can be easily ported to other versions and platforms.


  • Before running any of the examples, make sure you have installed the Vitis core development kit as described in Installation in the Application Acceleration Development flow of the Vitis Unified Software Platform Documentation (UG1416).

  • If you run applications on the Xilinx® Alveo™ Data Center accelerator cards, ensure the card and software drivers have been correctly installed by following the instructions To complete installation, follow the instructions on the Alveo Product Documentation tab.

Accessing the Tutorial Reference Files

  1. To access the reference files, type the following into a terminal: git clone https://github.com/Xilinx/Vitis-Tutorials.

  2. Navigate to the vitis_hls_analysis directory, and then access the reference-files directory.