2020.1 Vitis™ - Acceleration Tutorial for Alveo U50See Vitis™ Development Environment on xilinx.com |
make
* Run Vitis Analyzer to visualize the application timeline
* Run Vitis HLS to study kernel code performance and resource metrics
+ [**Vitis Module 2**](./03-Algorithm_Acceleration/docs/module2_pipeline/README.md) (short module to focus on the impact of PIPELINE
and INTERFACE
)
* Understanding instruction parallelism with the HLS PIPELINE
pragma
* Applying the INTERFACE
pragma to manage physical ports adapters
+ [**Vitis Module 3**](./03-Algorithm_Acceleration/docs/module3_datatype/README.md)
* Modify design to use the more hardware efficient C++ float
data types (compared to double
)
* Run Vitis, Vitis Analyzer and Vitis HLS
+ [**Vitis Module 4**](./03-Algorithm_Acceleration/docs/module4_dataflow/README.md)
* Apply the DATAFLOW
task parallelism optimization pragma
* Run Vitis, Vitis Analyzer and Vitis HLS (including viewing specific dataflow waveforms)
* Run on the U50 card
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