( FreqShift_0 ) = 0.9;
// create nets to specify connections
adf::connect< > net0 (In1, FIR_Halfband_Decimator1.in);
adf::connect< > net1 (FIR_Halfband_Decimator1.out, FIR_Halfband_Decimator2.in);
adf::connect< > net2 (FIR_Halfband_Decimator2.out, FIR_Halfband_Decimator3.in);
adf::connect< > net3 (FIR_Halfband_Decimator3.out, FIR_Symmetric_Filter.in);
adf::connect< adf::window<1024> > net4 (FIR_Symmetric_Filter.out, FreqShift_0.in[0]);
adf::connect< adf::window<1024> > net5 (FreqShift_0.out[0], Out1);
}
};
#endif // __XMC_FIRCHAIN_H__
```
Finally, the bit-exact simulation (Emulation-AIE) is performed and the result compared to the Simulink simulation:
![missing image](Images/Image_012.png)
Vitis Analyzer is then launched. From here you can see the **Graph View**, the **Array View**, the **Timeline**, and the **Profile** information.
![missing image](Images/Image_022.png)
![missing image](Images/Image_023.png)
## Conclusion
Model Composer is a very efficient way to create graphs either using your own kernels or using the DSPLib FIR Filter (other blocks will be available in subsequent releases).
This tool shows its incredible flexibility when it comes to display spectrum or save data at any stage of the graph. All the source and sink blocks can be used anywhere, allowing you to efficiently debug your design in all corner cases.
---
© Copyright 2021 Xilinx, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
```
http://www.apache.org/licenses/LICENSE-2.0
```
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
XD058 | © Copyright 2021 Xilinx, Inc.