interface
pragma to explicitely describe the connectivity and settings for the C ports of the kernel.
### Pipelining for Throughput
High-level synthesis can be very conservative by default, for example loop body instructions are entirely executed at each iteration instead of executing in a staggered fashion. That latter style of execution is explicitely enabled by the PIPELINE
pragma, it then reduces the initiation interval (II) for a function or loop (here in this tutorial, it's applied on loops) by allowing the concurrent execution of the different operations.
A pipelined function or loop can then process new inputs every PIPELINE
pragma is 1, which processes a new input every clock cycle. You can also specify the initiation interval through the use of the II option.
Pipelining a loop allows its operations to be implemented so that these operations execute concurrently as shown in the following animated figure below. In that example and by default there are 3 clock cycles between each input read (so II=3), and it requires 12 clock cycles fully execute the loop compared to 6 when the pragma is used.
![Pipeline](../images/anim_pipeline.gif)
If the Vitis high-level synthesis tool cannot create a design with the user-specified II, it issues a warning and creates a design with the lowest achievable II.
You can then analyze this design with the warning message to determine what steps must be taken to create a design that satisfies the required initiation interval.
To enable the pragma in the C source, insert it within the body of the function or loop.
```cpp
#pragma HLS pipeline II=foo
is pipelined with an initiation interval of 1:
```cpp
void foo { a, b, c, d} {
#pragma HLS pipeline II=1
...
}
```
Take a look at the kernel source code and notice how the PIPELINE
pragma/directive is applied for several loops in the code.
Since Vitis HLS automatically pipelines the most inner loops, the results won't be different compared to what was seen in the previous module (the baseline).
### The INTERFACE
Pragma
The INTERFACE
pragma specifies the physical adapters for the kernel C ports and how they attach to the platform during what's referred to as "interface synthesis" in HLS.
These physical adapters and their associated RTL implementation are derived from the following:
- Any function-level protocol that is specified: Function-level protocols, also called block-level I/O protocols, provide signals to control when the function starts operation, and indicate when function operation ends, is idle, and is ready for new inputs. The implementation of a function-level protocol is: Specified by the INTERFACE
pragma is used on sub-functions, only the register option can be used. The Copyright© 2020-2021 Xilinx