############################################################################## Runtime and System Optimization Tutorials ############################################################################## .. sidebar:: More Information See Vitis™ Development Environment on `xilinx.com `_ *********************************************** Design Tutorials *********************************************** .. toctree:: :maxdepth: 3 :caption: Design Tutorials :hidden: XRT Host Code Optimization <./Design_Tutorials/01-host-code-opt/README> The methodology for developing optimized accelerated applications is comprised of two major phases: architecting the application, and developing the hardware kernels. In the first phase, you make key decisions about the application architecture by determining which software functions should be accelerated onto FPGA kernels, how much parallelism can be achieved, and how to deliver it in code. In the second phase, you implement the kernels by structuring the source code, and applying the necessary compiler options and pragmas to create the kernel architecture needed to achieve the optimized performance target. The following examples illustrate the use of this methodology in real-world applications. .. list-table:: :widths: 20 80 :header-rows: 1 * - Tutorial - Description * - :doc:`XRT Host Code Optimization <./Design_Tutorials/01-host-code-opt/README>` - Train, prune, and quantize a modified version of the AlexNet convolutional neural network (CNN) with the Kaggle Dogs vs. Cats dataset in order to deploy it on the Xilinx ZCU102 board. *********************************************** Feature Tutorials *********************************************** .. toctree:: :maxdepth: 3 :caption: Design Tutorials :hidden: Using Multiple DDR Banks <./Feature_Tutorials/01-mult-ddr-banks/README> Using Multiple Compute Units <./Feature_Tutorials/02-using-multiple-cu/README> Controlling Vivado Implementation <./Feature_Tutorials/03-controlling-vivado-implementation/README> Optimizing for HBM <./Feature_Tutorials/04-using-hbm/README> Feature tutorials illustrate specific workflows or stages within Vitis AI. .. list-table:: :widths: 20 80 :header-rows: 1 * - Tutorial - Description * - :doc:`Using Multiple DDR Banks <./Feature_Tutorials/01-mult-ddr-banks/README>` - This tutorial demonstrates how using multiple DDRs can improve data transfer between kernels and global memory. * - :doc:`Using Multiple Compute Units <./Feature_Tutorials/02-using-multiple-cu/README>` - This tutorial demonstrates the flexible kernel linking process to increase the number of kernel instances on an FPGA, which improves the parallelism in a combined host-kernel system. * - :doc:`Controlling Vivado Implementation <./Feature_Tutorials/03-controlling-vivado-implementation/README>` - This tutorial demonstrates how you can control the Vivado® tools flow when implementing your project. * - :doc:`Optimizing for HBM <./Feature_Tutorials/04-using-hbm/README>` - This tutorial demonstrates how you can take best advantage of HBM on platforms that support it.