( FreqShift_0 ) = 0.9;
// create nets to specify connections
adf::connect< > net0 (In1, FIR_Halfband_Decimator.in);
adf::connect< > net1 (FIR_Halfband_Decimator.out, FIR_Halfband_Decimator1.in);
adf::connect< > net2 (FIR_Halfband_Decimator1.out, FIR_Halfband_Decimator2.in);
adf::connect< > net3 (FIR_Halfband_Decimator2.out, FIR_Symmetric.in);
adf::connect< adf::window<1024> > net4 (FIR_Symmetric.out, FreqShift_0.in[0]);
adf::connect< adf::window<1024> > net5 (FreqShift_0.out[0], Out1);
}
};
class FIRchain : public adf::graph {
public:
FIRchain_base mygraph;
public:
adf::input_plio In1;
adf::output_plio Out1;
FIRchain() {
In1 = adf::input_plio::create("In1",
adf::plio_32_bits,
"./data/input/In1.txt");
Out1 = adf::output_plio::create("Out1",
adf::plio_32_bits,
"Out1.txt");
adf::connect< > (In1.out[0], mygraph.In1);
adf::connect< > (mygraph.Out1, Out1.in[0]);
}
};
#endif // __XMC_FIRCHAIN_H__
```
Finally, the bit-exact simulation (Emulation-AIE) is performed and the result compared to the Simulink simulation:
![missing image](Images/Image_012.png)
Vitis Analyzer is then launched. From here you can see the **Graph View**, the **Array View**, the **Timeline**, and the **Profile** information.
![missing image](Images/Image_022.png)
![missing image](Images/Image_023.png)
The Simulation Data Inspector opens-up and we can see the output frames and the estimate of the output throughput as shown below:
![missing image](Images/Image_024.png)
Here the estimated throughput is 44 MSPS instead of the expected 100 MSPS. You can use Vitis Analyzer to track the reason of this throughput reduction. Here it is very easy to see that the input stream feeds the data @250 MSPS instead of the 800 MSPS that were expected in the graph. The reason is that the input bitwidth is 32 bits at a rate of 250MHz (default value) as can be seen at the end of the FIRchain.h file.
## Stage 4: Increasing PLIO bitwidth and re-generate
Solving this problem is fairly easy. Navigate inside the **FIRchain** sub-system. Get the **PLIO** block from **Xilinx Toolbox / AI Engine / Interface** or just type **plio** in the canvas. Double-click on the new block and specify:
- **PLIO width (bits)**: 128
- Check **Specify PLIO frequency**
- **PLIO frequency (MHz)** : 250
Click **OK**. Place the block just after the input port, and a copy of this block just before the output port:
![missing image](Images/Image_025.png)
Re-open the **Vitis Model Composer Hub** and click **Generate** to re-compile and re-simulate the design.
After the AI Engine simulation, the estimated throughput is 177 MSPS. This is computed from the following timestamped (green) output data:
![missing image](Images/Image_026.png)
Three frames are received but only two interframe idle time are taken into account. A more precise estimate woul be to count the 512 output samples in between the 2 red vertical line. This gives almost 125 MSPS which is 1/8th of the input sample rate (1 GSPS). This means that the design can support for sure the 800 MSPS that were specified in the design.
## Conclusion
Model Composer is a very efficient way to create graphs either using your own kernels or using the DSPLib FIR Filter (other blocks will be available in subsequent releases).
This tool shows its incredible flexibility when it comes to display spectrum or save data at any stage of the graph. All the source and sink blocks can be used anywhere, allowing you to efficiently debug your design in all corner cases.
---
© Copyright 2021-2022 Xilinx, Inc.
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
```
http://www.apache.org/licenses/LICENSE-2.0
```
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
XD058 | © Copyright 2021-2022 Xilinx, Inc.