Vitis™ Hardware Acceleration Tutorials

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Vitis Hardware Acceleration on Cholesky Algorithm

Version: Vitis 2022.1

This tutorial is divided in 3 sections.

  • Section 1 (~10 mins):

    • An overview of Vitis and the host/kernel paradigm

      • See how Vitis takes care of the heavy lifting to let you focus on the application code

  • Section 2 (a couple of minutes if Alveo U50 card is already installed):

    • Setup the Vitis development tools

    • Detect and check the card installed on the server

  • Section 3 (a few hours):

    • Understand the Cholesky algorithm and run it on the CPU first

    • Re-organize the code to create both a host and a kernel program

    • Review the APIs that bind the host and the kernel

    • Apply incremental optimizations to the kernel across several modules to improve throughput. Finally program the Alveo card with the fully optimized accelerator to verify the performance

    • Introduction

      • Meet the Cholesky algorithm!

      • Run a CPU version

    • Vitis Module 1

      • Get a performance baseline as a reference point with a first kernel design

      • Run Vitis in GUI mode or via make

      • Run Vitis Analyzer to visualize the application timeline

      • Run Vitis HLS to study kernel code performance and resource metrics

    • Vitis Module 2 (short module to focus on the impact of PIPELINE and INTERFACE)

      • Understanding instruction parallelism with the HLS PIPELINE pragma

      • Applying the INTERFACE pragma to manage physical ports adapters

    • Vitis Module 3

      • Modify design to use the more hardware efficient C++ float data types (compared to double)

      • Run Vitis, Vitis Analyzer and Vitis HLS

    • Vitis Module 4

      • Apply the DATAFLOW task parallelism optimization pragma

      • Run Vitis, Vitis Analyzer and Vitis HLS (including viewing specific dataflow waveforms)

      • Run on the U50 card

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