Vitis™Hardware Acceleration Introduction Tutorial

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Version: Vitis 2022.1

Xilinx FPGAs and Versal ACAP devices are uniquely suitable for low-latency acceleration of high performance algorithms and workloads. With the demise of traditional Moore’s Law scaling, design-specific architectures(DSAs) are becoming the tool of choice for developers needing the optimal balance of capability, power, latency, and flexibility. But, approaching FPGA and ACAP development from a purely software background can seem daunting.

With this set of documentation and tutorials, our goal is to provide you with an easy-to-follow, guided introduction to accelerating applications with Xilinx technology. We will begin from the first principles of acceleration: understanding the fundamental architectural approaches, identifying suitable code for acceleration, and interacting with the software APIs for managing memory and interacting with the target device in an optimal way.

This set of documents is intended for use by software developers, it is not a low-level hardware developer’s guide. The topics of RTL coding, low-level FPGA architecture, high-level synthesis optimization, and so on are covered elsewhere in other Xilinx documents. Our goal here is to get you up and running with Vitis quickly, with the confidence to approach your own acceleration goals and grow your familiarity and skill with Xilinx over time.

Provided Design Files

In this directory tree you will find a collection of documents and a directory named design_source. The design_source directory contains all of the design elements - hardware and software - for the tutorial you’re currently reading. The example applications correspond to specific sections in the guide. Every effort has been made to keep the code samples as concise and “to the point” as possible.

Table of Contents

This tutorial is divided into several discrete example desings. Note that each design builds on the last one, so if this is your first time here we recommend proceeding through the tutorial in order.

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