Vitis Hardware Acceleration Tutorials

See Vitis™ Development Environment on xilinx.com

Hardware Acceleration Tutorials¶

Introduction to Vitis Hardware Acceleration¶

Tutorial	Description
Introduction to Vitis Hardware Acceleration	This tutorial provides you with an easy-to-follow, guided introduction to accelerating applications with Xilinx technology. We will begin from the first principles of acceleration: understanding the fundamental architectural approaches, identifying suitable code for acceleration, and interacting with the software APIs for managing memory and interacting with the target device in an optimal way.

Design Tutorials¶

The methodology for developing optimized accelerated applications is comprised of two major phases: architecting the application, and developing the hardware kernels. In the first phase, you make key decisions about the application architecture by determining which software functions should be accelerated onto FPGA kernels, how much parallelism can be achieved, and how to deliver it in code. In the second phase, you implement the kernels by structuring the source code, and applying the necessary compiler options and pragmas to create the kernel architecture needed to achieve the optimized performance target. The following examples illustrate the use of this methodology in real-world applications.

Tutorial	Description
Bloom Filter Example	This tutorial shows how to achieve a 10x speed-up on a data analytics application using a combination of kernel and host code optimization techniques.
Convolution Example	This tutorial walks through the process of analyzing and optimizing a 2D convolution used for real-time processing of a video stream.
RTL Systems Integration Example	This tutorial demonstrates how to integrate free-running RTL kernels, Vitis Library functions, and custom Vitis HLS kernels into a real system.
Traveling Salesperson Problem	This tutorial demonstrates the full flow to implement a HLS kernel from algorithm model to hardware.
Bottom RTL Kernel Design Flow Example	This tutorial demonstrates how to develope a complex RTL kernel from scratch via batch mode without GUI environment.
Choleskey Algorithm Acceleration	This tutorial puts in practice the concepts of FPGA acceleration and illustrates how to gradually optimize a hardware accelerator implementing the Cholesky matrix decomposition algorithm.
XRT Host Code Optimization	This tutorial demonstrates how to optimize your CPU host code to get the most out of interaction between your hardware accelerators and your runtime software.
Aurora Kernel on Alveo	This tutorial demonstrates how to integrate Aurora IP in user design on Alveo card with Vitis flow to realize high-speed inter-card communications.

Feature Tutorials¶

Tutorial	Description
Getting Started with RTL Kernels	This tutorial demonstrates how to use the Vitis core development kit to program an RTL kernel into an FPGA and build a Hardware Emulation using a common development flow.
Mixing C and RTL	This tutorial demonstrates how to work with an application containing RTL and C kernels, along with various design analysis features.
Dataflow Debug and Optimization	This tutorial demonstrates how to debug and optimize the dataflow optimization in Vitis HLS.
Using Multiple DDR Banks	This tutorial demonstrates how using multiple DDRs can improve data transfer between kernels and global memory.
Using Multiple Compute Units	This tutorial demonstrates the flexible kernel linking process to increase the number of kernel instances on an FPGA, which improves the parallelism in a combined host-kernel system.
Controlling Vivado Implementation	This tutorial demonstrates how you can control the Vivado® tools flow when implementing your project.
Optimizing for HBM	This tutorial demonstrates how you can take best advantage of HBM on platforms that support it.
Host Memory Access	This tutorial demonstrates how kernels can directly access buffers host memory directly. This capability requires a compatible platform.
Using GT Kernels and Ethernet IPs on Alveo	This tutorial demonstrates how to use networking GT kernels with generated Ethernet IPs and implement them on Alveo card with Vitis flow.