[min:max]`.
1. Define the `sp` command options for the vadd kernel and add this to the Makefile.
The kernel instance name will be: `vadd_1`.
The arguments for the vadd kernel are specified in the `vadd.cpp` file. The kernel argument (`in1`, `in2`, and `out`) should be connected to `DDR[0]`, `DDR[1]`, and `DDR[2]`.
Therefore, the `sp` options should be:
```
sp = vadd_1.in1:DDR[0]
sp = vadd_1.in2:DDR[1]
sp = vadd_1.out:DDR[2]
```
* Argument `in1` accesses DDR Bank0
* Argument `in2` accesses DDR Bank1
* Argument `out` accesses DDR Bank2.
The three `sp` options are added in `connectivity.cfg` file and you need to modify the Makefile to use that config file.
2. Open the Makefile and comment line 18, and uncomment line 19 to add the config file into `v++` linker options:
```
# Linker options to map kernel ports to DDR banks
#VPP_LINK_OPTS := --profile.data all:all:all
VPP_LINK_OPTS := --config connectivity.cfg
```
Using config files is a feature for the Vitis software platform. You can put options into different files and use `--config` to include them in a build.
3. After you have saved the changes, complete a clean build of the design in HW Emulation mode.
```bash
make clean
make all LAB=run2
```
Again, observe the messages in the Console view during the link step; a message similar to the following displays.
```
ip_name: vadd
Creating apsys_0.xml
INFO: [CFGEN 83-0] Port Specs:
INFO: [CFGEN 83-0] kernel: vadd_1, k_port: in1, sptag: DDR[0]
INFO: [CFGEN 83-0] kernel: vadd_1, k_port: in2, sptag: DDR[1]
INFO: [CFGEN 83-0] kernel: vadd_1, k_port: out, sptag: DDR[2]
INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.in1 to DDR[0] for directive vadd_1.in1:DDR[0]
INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.in2 to DDR[1] for directive vadd_1.in2:DDR[1]
INFO: [CFGEN 83-2228] Creating mapping for argument vadd_1.out to DDR[2] for directive vadd_1.out:DDR[2]
```
This confirms that the Vitis core development kit has correctly mapped the kernel arguments to the specified DDR banks from the `--sp` options provided.
4. Run HW-Emulation, and verify the correctness of the design.
```bash
make run LAB=run2
```
After the simulation is complete, you can see the memory connections for the kernel data transfer reported as follows.
```
TEST PASSED
INFO: [Vitis-EM 22] [Wall clock time: 23:15, Emulation time: 0.054906 ms] Data transfer between kernel(s) and global memory(s)
vadd_1:m_axi_gmem0-DDR[0] RD = 0.391 KB WR = 0.000 KB
vadd_1:m_axi_gmem1-DDR[1] RD = 0.391 KB WR = 0.000 KB
vadd_1:m_axi_gmem2-DDR[2] RD = 0.000 KB WR = 0.391 KB
```
You can also open the `vadd.hw_emu.xclbin.run_summary` and look at the Profile Summary to examine the **Kernel to Global Memory** section showing data transfers.
```bash
vitis_analyzer vadd.hw_emu.xclbin.run_summary
```
You will see the DDR banks assigned to each of the kernel arguments along with the traffic on each of the interfaces during HW-Emulation.
![missing image](./images/mult-ddr-banks_img_vitis.png)
### Conclusion
This tutorial showed you how to change the default mapping of ports `in1`, `in2`, and `out` of kernel vadd from a single DDR bank to multiple DDR banks. You also learned how to:
* Set `v++` linker options using the `--sp` switch to bind kernel arguments to multiple DDR banks.
* Build the application, and verify DDR mapping.
* Run HW-Emulation and observe the transfer rate and bandwidth utilization for each port.
Return to Main Page
Copyright© 2021-2022 Xilinx