Post-Link Recompile of an AI Engine Application

Lab 1: Direct AI Engine Recompile Makefile Flow

Initialization

All labs rely on a set of source files that are available in the Files sub-directory:

  • AIE contains the source files for the AI Engine application.

  • AIE2 contains the source files for the AI Engine application with location constraints for one of the AI Engine kernels.

  • Constraints contains the PLIO constraints file for the second phase.

  • data contains data files used to verify application functionality.

  • HwLink contains a system configuration file to link AI Engine and PL kernels.

  • PL contains all PL kernels (mm2s, s2mm, and polar_clip).

  • PS contains the host (A72) application that runs the PL kernels, launches the graph, and verifies the output.

Go to the Lab directory:

cd WithoutIntermediatePlatform

Phase 2: Recompile the AI Engine Application, Package the New System, and Rerun Hardware Emulation

AI Engine compilation in phase 1 generates numerous files in the Work directory. The Work/temp/graph_aie_routed.aiecst file contains all the constraints that can be used during AI Engine compilation to get the exact same placement. From this file, extract the constraints related to the PLIO interface nodes, removing the other nodes and all the port constraints:

{
  "NodeConstraints": {
    "DataIn1": {
      "shim": {
        "column": 24,
        "channel": 0
      }
    },
    "clip_in": {
      "shim": {
        "column": 24,
        "channel": 0
      }
    },
    "clip_out": {
      "shim": {
        "column": 25,
        "channel": 0
      }
    },
    "DataOut1": {
      "shim": {
        "column": 25,
        "channel": 0
      }
    }
  }
}

Phase 2 contains the following stages:

  1. aie2: As in the previous phase, this stage builds an AI Engine application, but in this case it uses the new interface constraints. The kernel itself has not changed but a kernel location constraint has been added to the graph so that you can see a big difference in the kernel placement. Check this new placement using Vitis Analyzer on the compile summary.

  2. package2: Create the PDI to load onto the device (hw_emu).

  3. run_emu: Launch the simulation and verify that the output is still correct.

Run make phase2 to go over all steps. Simulation is done in the same way as in phase 1, but it takes more time due to the longer routing path.

Perform On-Board Testing

  1. To perform on-board testing, the same stages can be replicated but with a different target:

  • For phase 1, type make TARGET=hw clean phase1.

  • For phase 2, type make TARGET=hw phase2.

  1. When the two phases are completed, there will be a sd_card.img file in the directory. Use a standard SD card imager with this file to initialize an SD card.

  2. Place the SD card in the top SD card slot of your board.

  3. Open a serial terminal connected to the right COM port of your VCK190 and switch on your board.

  4. The system boots. When this is finished, change the directory before launching the PS application.

cd /run/media/mmcblk0p1
./host.exe a.xclbin

Support

GitHub issues will be used for tracking requests and bugs. For questions go to forums.xilinx.com.

License

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.

You may obtain a copy of the License at http://www.apache.org/licenses/LICENSE-2.0

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.

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