Port Width Widening

This example shows how HLS introduces the capability of resizing the port width of the kernel interface ports for better resource utilization maintaining the performance.

KEY CONCEPTS: Interface port width auto widening

KEYWORDS: m_axi_max_widen_bitwidth

This example introduces the capability of how Vitis HLS can configure the size of kernel interface ports.

User can customize the interface ports size using ‘config_interface -m_axi_max_widen_bitwidth size’ Following is the content of hls_config.tcl file

config_interface -m_axi_max_widen_bitwidth 256

The interface size setting need to be specified in hls_config.tcl file. We include this tcl file in our krnl_port_widen.ini file and by using the --config tag in the kernel compile stage we specify the m_axi interface size.

Following is the content of ini file

[advanced]
prop=solution.hls_pre_tcl=hls_config.tcl

Below are the resource numbers while running the design on U200 platform :

Design	port_size	BRAM	DSP	FF	LUT
krnl_base	512	32	3	6331	4205
krnl_widen	256	18	3	4006	3452

DESIGN FILES

Application code is located in the src directory. Accelerator binary files will be compiled to the xclbin directory. The xclbin directory is required by the Makefile and its contents will be filled during compilation. A listing of all the files in this example is shown below

src/host.cpp
src/krnl_base.cpp
src/krnl_widen.cpp

COMMAND LINE ARGUMENTS

Once the environment has been configured, the application can be executed by

./port_width_widening <krnl_port_widen XCLBIN>