C++ Kernels

This page contains examples for users who are new to Xilinx Vitis OpenCL Flows. The focus of the examples is towards code optimization using HLS C/C++ kernels for Xilinx devices.

List of Examples

• Array Partition
• AXI Burst Performance
• Burst Read/Write
• BIND OP and STORAGE
• Critical Path
• Custom Data Type
• Dataflow Using HLS Stream
• Dataflow Using Array of HLS Stream
• Loop Dependency Inter
• Global Memory Two Banks
• Stream Chain Matrix Multiplication
• Kernel Global Bandwidth
• Local Memory Two Parallel Read/Write
• Loop Pipelining
• Loop Reordering
• Array Block and Cyclic Partitioning
• Port Width Widening
• PLRAM Memory Access
• Vector Addition
• Shift Register
• Systolic Array
• Wide Memory Read/Write