Verifiable Delay Function

Overview

A Verifiable Delay Function (VDF) is a function whose evaluation requires running a given number of sequentialsteps, yet the result can be efficiently verified. Here implement two VDFs: Efficient verifiable delay functions (Wesolowski) and Simple Verifiable Delay Functions (Pietrzak). Its algorithm is defined in REF Wesolowski and REF Pietrzak.

Implementation on FPGA

There are 3 APIs provided that are evaluate, verifyWesolowski, and verifyPietrzak. The APIs are completely implemented according to the algorithm of the above reference paper, except that the multiplication of large-bit-width integers is implemented based on “Montgomery Production”. For “Montgomery Production”, please refer to REF monProduct for details.