 ZCU670 Evaluation Kit Tutorial |
Hardware Architecture of the PTP Packet Processor |
Hardware Architecture of the PTP Packet Processor¶
The PL based PTP Packet processors present in the datapaths of receive and transmit direction is used to Timestamp the packets while entering and leaving the system respectively.
PTP Tx HW MASTER IP¶
The PTP HW Master receives the necessary information from the USER-APP fields of the AXI MCDMA for capturing timestamp and storing it in the memory for the Transmitted PTP packets. The address of the memory where the timestamp needs to be stored is provided by the USER-APP fields of AXI MCDMA Control stream. The SW provides a 2-bit PTP flag. Based on the value of the Flag bits, the PTP HW Master drives the tx_ptp_1588op_in [1:0] interface of MRMAC. MRMAC performs the PTP operation based on the 2 bit value of tx_ptp_1588op_in[1:0] as given in below table:
| tx_ptp_1588op_in [1:0] | Operation |
|---|---|
| 2’b00 | No operation: no timestamp is taken, and the frame is not modified. |
| 2’b10 | 2-step: a timestamp should be taken and returned to the client using the additional ports of 2-step operation. The frame itself is not modified. |
| 2’b11 | Reserved |
The PTP HW Master in the zcu670 TRD supports 2-step PTP mode of operation.
2-step Mode:
When the ptp flag value is “10”, the PTP HW Master initiates a memory write operation of the timestamp received from Timer syncer IP. The timestamp value is written into the memory via a AXI memory mapped interface. The PTP HW Master sets a bit to 1 to indicate the completion of memory write to Software.
Rx PTP PACKET DETECT and PREPEND LOGIC IP¶
PTP Packet Detection IP parses all the received Packets.
When a PTP packet is received, it parses the Header and sets a PTP Qualifier bit to ‘1’ when a PTP packet is detected, that helps the PTP application in upper layer for further processing.
PTP detect logic detects PTP packets considering the following PTP transport mechanism.
Supported Features:
PTP Packet over IEEEE 802.3
PTP Packet over UDP IPV4 – Version 1 and Version 2
The PTP detect logic checks the Type field of the received packet whenever a new ethernet packet is received and also checks for the multicast IP destination address for UDP IPV4 Packets, to carry out the PTP detection and sets the PTP Packet Qualifier bit - DW_1[31]
Timestamp prepend logic prepends two 64 bit Datawords (128 bit) to all the received packets, which has 80 bit Timestamp information and the status of the Qualifier bit. Below table has the details of prepended datawords.
| Status words | Content |
|---|---|
| Prepended DW_0 | 63 : 0 - Timestamp[63:0] |
| Prepended DW_1 | 15 : 0 - Timestamp[79:64] 30 : 16 - Reserved 31 - PTP Packet Qualifier bit 63 : 32 - Reserved |
| DW-2 | Received Packet data stream starts |
Next Steps
Go to the SW Architecture Platform page
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