# AMR RAVE - Base Logic
> **For common base design concepts**, see [Common Base Design Philosophy](../hardware/base-logic.md)
>
> This document describes the RAVE (VE2302) base logic implementation.
## Overview
The RAVE base logic implementation provides PCIe connectivity and basic management functionality through programmable logic IP blocks. The VE2302 device requires PL-based PCIe and XDMA IP because it does not include a CPM (Coherent PCIe Module) hardened block.
The base design includes the PCIe Versal IP for Gen3 x4 connectivity to the on-board Ryzen processor, along with the XDMA PL IP providing DMA functionality. This implementation consumes programmable logic resources to deliver PCIe and DMA capabilities that would otherwise be provided by hardened silicon in devices with CPM blocks.
The design follows the minimal base design philosophy common across AMR boards, with management handled primarily through firmware running on the RPU rather than dedicated hardware IP blocks in the programmable logic.
## VE2302 Device Architecture
The VE2302 is a Versal Edge-series device optimized for embedded applications with a balance of performance, power, and cost. The Edge series devices focus on integration of essential features while maintaining lower power consumption compared to larger Versal devices.
The VE2302 includes GTYP transceivers capable of Gen3 PCIe operation for connectivity to the host processor and expansion interfaces.
Since the Edge series does not include CPM or HBM blocks, the design must implement PCIe functionality using IP instantiated in the programmable logic fabric. This approach provides flexibility in configuration while requiring careful attention to resource usage and timing closure.
## PCIe IP Implementation
The RAVE design instantiates the PCIe Versal IP (xilinx.com:ip:pcie_versal) to provide Gen3 x4 PCIe connectivity. The IP is configured for two physical functions following the standard AMR pattern where PF0 provides management functionality and PF1 provides user and DMA functionality.
The PCIe IP connects to GTYP transceivers for the x4 link. Reference clocks are provided by external oscillators. The link operates at 8.0 GT/s providing approximately 4 GB/s of raw bandwidth.
The IP generates device IDs 0x5700 for PF0 and 0x5701 for PF1, using vendor ID 0x10EE and subsystem ID 0x000e. Both functions are configured with base class 12 (Processing Accelerators) and subclass 00.
## XDMA PL IP Implementation
The XDMA PL IP (xilinx.com:ip:xdma) provides the DMA engine for data transfer between the host and device memory. The IP supports multiple DMA channels with memory-mapped and streaming interfaces.
The XDMA configuration uses 2 physical functions (PF0 for management with device ID 0x5710, PF1 for user/DMA with device ID 0x5711). The IP provides AXI-Lite master interface for register access, AXI bypass interface for memory-mapped access, and streaming interfaces for high-performance data transfer. Function Level Reset is disabled in both the XDMA IP and PCIe IP configuration.
The XDMA IP along with the PCIe IP consumes programmable logic resources for PCIe and DMA functionality. This represents a significant portion of the available programmable logic resources and must be accounted for in the overall design resource budget.
## PF0 Configuration
The PF0 physical function provides management functionality with device ID 0x5700. The function is configured in the PCIe IP with base class 12 and subclass 00, maintaining consistency with the AMR management function pattern.
The PF0 BAR configuration provides address space for management register access. The specific BAR sizes are configurable in the PCIe IP based on the management requirements. The base design reserves this address space for future expansion but does not instantiate management hardware IP blocks in the programmable logic.
Management operations are handled through firmware running on the RPU, which accesses board resources through CIPS-integrated peripherals including I2C for sensors and EEPROMs, SPI for flash operations, and UART for debug interfaces.
## PF1 Configuration
The PF1 physical function supports both DMA operations and AXI bridge access to programmable logic peripherals. The function uses device ID 0x5701 and is configured with appropriate BARs for DMA register access and PL peripheral access.
The XDMA IP provides the DMA functionality through its channel-based architecture. DMA channels support memory-mapped and streaming data transfer, with configuration managed through the XDMA control registers accessible via BAR space.
The PF1 hierarchy typically includes test infrastructure similar to other AMR boards, with a SmartConnect providing AXI interconnect functionality, an AXI GPIO block for loopback testing, and processor system reset blocks for reset synchronization.
## NoC Integration
The PCIe and XDMA IP blocks connect to the NoC through NMU_512 (NoC Master Unit) and NSU_512 (NoC Slave Unit) interfaces instantiated in the AXI NoC IP. This soft logic NoC connection differs from hardened NMU_128 connections used by CIPS blocks.
The XDMA M_AXI master interface connects through an NMU_512 to route DMA traffic to the LPDDR4 memory controllers. The AXI NoC IP configuration includes QoS settings specifying the bandwidth requirements, with typical values of 800 MB/s or higher depending on the application needs. The NoC compiler uses these QoS specifications to determine the optimal routing through the NoC fabric.
Clock domain crossing is handled within the AXI NoC IP, allowing the XDMA and PCIe IP to operate in their respective clock domains while interfacing with the NoC's clock domain. The NoC supports asynchronous interfaces and includes the necessary synchronization logic.
## Programmable Logic Resource Usage
The RAVE base design requires substantial programmable logic resources to implement the PCIe and DMA functionality. The resource usage includes the PCIe Versal IP and the XDMA IP for the PCIe infrastructure.
Additional resources are required for the test hierarchy including SmartConnect, AXI GPIO, and processor system reset blocks. When clock generation IP is added for custom clock domains, this adds further to the resource count.
Block RAM and UltraRAM usage varies based on the specific XDMA configuration and additional IP blocks instantiated in the design.
These resource requirements must be considered when planning user applications, as they reduce the available logic, memory, and routing resources for application-specific IP blocks and logic.
## Expansion Header Integration
The RAVE Board provides an expansion connector for application-specific daughtercards. The connector brings out GT transceivers, XPIO signals, and HDIO signals from the VE2302 device for custom I/O interfaces.
**Note:** For connector specifications and pinout details, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) and hardware design repository.
## Peripheral Integration
The RAVE Board includes several on-board peripherals not typically found in pure FPGA accelerator cards. These peripherals support standalone embedded system operation and board management functions.
The board includes a Board-ID EEPROM accessible via I2C at address 0x57. This EEPROM stores board identification information, manufacturing data, and Board-specific configuration. The firmware accesses this EEPROM through the CIPS I2C peripheral to read board identity and configuration during boot.
A TPM 2.0 security module connects via SPI, providing hardware-based cryptographic operations and secure key storage. This enables secure boot, platform attestation, and other security features required in automotive and industrial applications.
A USB-to-UART bridge provides multiple serial interfaces accessible from the host system via USB, simplifying debug and console access.
Status LEDs are connected to MIO pins providing visual indication of system state, boot progress, and application status. The firmware controls these LEDs through MIO GPIO registers.
Some board variants include additional peripherals such as eMMC storage and USB 2.0 host controller via Versal MIO.
**Note:** For peripheral specifications and part numbers, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html).
## Design Complexity and Timing
Implementing PCIe and XDMA in programmable logic introduces additional design complexity compared to using hardened blocks. The soft logic implementation requires careful floorplanning to meet timing requirements, particularly for the high-speed PCIe interfaces and the wide AXI data paths.
The NoC routing must be configured to efficiently handle the DMA traffic from the XDMA IP to the memory controllers. The AXI NoC IP configuration includes bandwidth specifications and QoS settings that the NoC compiler uses to determine optimal routing paths through the device.
Clock domain crossings between the PCIe clock domain, the XDMA clock domain, and the NoC clock domain require proper synchronization through processor system reset blocks. Multiple reset synchronization blocks may be instantiated to handle the various clock domains present in the design.
The GT transceiver configuration for PCIe requires attention to reference clock quality, signal integrity, and proper PCB design. The GTYP transceivers must be configured for Gen3 operation with appropriate equalization and receiver settings to ensure reliable link operation.