# AMR RAVE - CIPS Configuration

> **For common CIPS concepts**, see [Common CIPS Configuration](../hardware/cips-config.md)
>
> This document describes RAVE (VE2302) CIPS configuration without CPM.

<span id="amrrave-cipsconfiguration-overview"></span>

## Overview

The RAVE CIPS configuration focuses on the Processing System (PS), Platform Management Controller (PMC), and peripheral setup. The VE2302 device does not include a CPM block, so there is no CPM_CONFIG section in the CIPS settings. PCIe functionality is instead provided by PL-based IP blocks.

<span id="amrrave-cipsconfiguration-ve2302device"></span>

## VE2302 Device Configuration

The VE2302 is a Versal Edge-series device optimized for embedded applications. The CIPS configuration enables the essential processing blocks and peripherals while omitting features not present in Edge-series devices.

**CIPS Blocks Configured:**
- RPU (Realtime Processing Unit) for firmware
- PMC (Platform Management Controller) for boot/config
- PS peripherals (I2C, SPI, UART, USB, eMMC)
- NoC connections (RPU to NoC, PMC to NoC)
- OSPI interface for boot flash

**Not Present in VE2302:**
- CPM (Coherent PCIe Module) - Use PL PCIe IP instead
- HBM - Edge devices do not include HBM

<span id="amrrave-cipsconfiguration-rpu"></span>

## RPU Configuration

The RPU configuration matches the common AMR pattern with two Arm Cortex-R5F processors used for firmware execution. The RPU handles board management, inter-processor communication, flash management, and host communication through the PCIe interface.

**RPU NoC Connection:**
- LPD_AXI_NOC_0: 128-bit @ 800MHz
- Purpose: RPU access to LPDDR4 memory
- Enable: PS_USE_NOC_LPD_AXI0 = 1

**M_AXI_LPD Interface:**
- Data Width: 32-bit
- Frequency: 100 MHz
- Status: Enabled but not connected in base design
- Purpose: Reserved for future management IP (SMBus, peripherals)
- Enable: PS_USE_M_AXI_LPD = 1

<span id="amrrave-cipsconfiguration-pmc"></span>

## PMC Configuration

The PMC manages boot and configuration with OSPI flash interface and NoC connectivity for memory access during initialization.

**PMC NoC Connection:**
- PMC_NOC_AXI_0: 128-bit @ 400MHz (SLR0)
- Purpose: PMC access to LPDDR4 during boot/config
- Enable: PS_USE_PMC_NOC_AXI0 = 1

**OSPI Configuration:**
- Interface: PMC Bank 500
- Flash: 128MB OSPI
- Frequency: 200 MHz
- Mode: Single (not stacked)
- Boot Mode: Custom (QSPI/OSPI)

<span id="amrrave-cipsconfiguration-peripherals"></span>

## Peripheral Configuration

### I2C Interfaces

**LPD_I2C0:**
- MIO Pins: PS_MIO 10-11
- Purpose: Board-ID EEPROM (0x57), sensors, PMICs
- Enable: PS_I2C0_PERIPHERAL

**PMC_I2C / LPD_I2C1:**
- Configuration varies by board
- Purpose: Additional I2C devices

### UART Interfaces

**UART0:**
- MIO Pins: PMC_MIO 16-17 or PS_MIO 8-9
- Purpose: Primary debug console
- Enable: PS_UART0_PERIPHERAL

**UART1:**
- MIO Pins: PMC_MIO 20-21 or PS_MIO 20-21
- Purpose: Secondary debug/logging
- Enable: PS_UART1_PERIPHERAL

### SPI Interfaces

**SPI (TPM):**
- MIO Pins: PMC Bank 501
- Purpose: TPM 2.0 security module access
- Enable: PMC SPI configuration

### Board-specific Peripherals

Some board variants include additional peripherals:

**USB 2.0 Host Controller:**
- Available on select variants
- Purpose: Front panel USB port
- Configuration: USB 2.0 host mode via Versal MIO

**eMMC Storage:**
- Available on select variants
- Purpose: On-device persistent storage
- Configuration: PMC_SD0 in eMMC mode

**Note:** For variant-specific peripheral availability and MIO pin assignments, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) and hardware design repository.

<span id="amrrave-cipsconfiguration-plclocks"></span>

## PL Reference Clocks

The CIPS generates three PL reference clocks:

| Clock | Frequency | Usage |
|-------|-----------|-------|
| **pl0_ref_clk** | 100 MHz | PL logic, SmartConnect, GPIO |
| **pl1_ref_clk** | 33.33 MHz | Clock wizard input (optional) |
| **pl2_ref_clk** | 250 MHz | NoC AXI interfaces |

**Configuration:**
- PMC_CRP_PL0_REF_CTRL_FREQMHZ: 100
- PMC_CRP_PL1_REF_CTRL_FREQMHZ: 33.3333333
- PMC_CRP_PL2_REF_CTRL_FREQMHZ: 250

<span id="amrrave-cipsconfiguration-plresets"></span>

## PL Resets

**pl0_resetn:**
- Count: 1 (PS_NUM_FABRIC_RESETS = 1)
- Purpose: Main PL reset output
- Usage: Drives proc_sys_reset blocks in PL

<span id="amrrave-cipsconfiguration-interrupts"></span>

## Interrupt Configuration

### PL-PS Interrupts

**LPD Interrupts (Optional):**
- IRQ 0-1: Configured but not connected in base design
- Purpose: Reserved for firmware events (GCQ signals, peripheral interrupts)
- Enable: PS_IRQ_USAGE configuration

### Inter-Processor Interrupts (IPI)

**IPI Agent Assignment:**
- IPI 0-2: PMC, PSM (default system)
- IPI 3-4: R5_0 (first R5 core)
- IPI 5-6: R5_1 (second R5 core)

Enable configuration:
- PS_GEN_IPI3_ENABLE: 1, PS_GEN_IPI3_MASTER: R5_0
- PS_GEN_IPI4_ENABLE: 1, PS_GEN_IPI4_MASTER: R5_0
- PS_GEN_IPI5_ENABLE: 1, PS_GEN_IPI5_MASTER: R5_1
- PS_GEN_IPI6_ENABLE: 1, PS_GEN_IPI6_MASTER: R5_1

<span id="amrrave-cipsconfiguration-pciereset"></span>

## PCIe Reset Configuration

**PCIe Reset Pins:**
- PMC_MIO_24: PCIe RST (fundamental reset)
- PMC_MIO_25: PCIe WAKE_B (wake signal)

These MIO pins connect to the PL PCIe IP for reset and power management signaling.

**Configuration:**
- PS_PCIE_RESET: Enable
- PS_PCIE_EP_RESET1_IO: PMC_MIO_24
- PMC_MIO_EN_FOR_PL_PCIE: Configuration for PL PCIe routing

<span id="amrrave-cipsconfiguration-mioconfiguration"></span>

## MIO Pin Configuration

MIO pins are configured for the following functions:

**PMC Bank 500:**
- OSPI flash interface
- UART0/UART1 (debug consoles)
- I2C interface
- PCIe control signals (reset, wake)
- Status LED

**PMC Bank 501:**
- Power control signals
- I2C1 interface
- SPI interface (TPM 2.0)

**LPD Bank 502:**
- Status LEDs (RPU controlled)
- I2C0 interface (Board-ID EEPROM at 0x57)
- ROM control signals
- Voltage monitors

**Note:** For complete MIO pin assignments and signal details, refer to the hardware design repository.

<span id="amrrave-cipsconfiguration-bootmode"></span>

## Boot Configuration

The VE2302 boots from OSPI flash with the PMC managing the boot sequence:

**Boot Mode Settings:**
- BOOT_MODE: Custom
- Primary Boot: OSPI (PMC Bank 500)
- Boot Mode Pins: Configured for QSPI/OSPI boot

**Boot Sequence:**
1. PMC loads PDI from OSPI flash
2. PMC initializes LPDDR4 memory controller
3. PMC loads RPU firmware from PDI
4. RPU firmware begins execution
5. RPU initializes peripherals and establishes PCIe communication

<span id="amrrave-cipsconfiguration-designmode"></span>

## Design Mode Settings

The CIPS uses custom design mode for full configuration control:

```tcl
DESIGN_MODE {1}
BOOT_MODE {Custom}
CLOCK_MODE {Custom}
DDR_MEMORY_MODE {Custom}
IO_CONFIG_MODE {Custom}
DEVICE_INTEGRITY_MODE {Custom}
```

These custom mode settings enable detailed configuration of all CIPS parameters specific to the RAVE hardware design.

<span id="amrrave-cipsconfiguration-pcieapertures"></span>

## PCIe Aperture Configuration

**Aperture Settings:**
- PCIE_APERTURES_SINGLE_ENABLE: 1
- PCIE_APERTURES_DUAL_ENABLE: 0

Single aperture mode is used for PCIe address mapping through the NoC to memory and PL address spaces.

## References

- [Common CIPS Configuration](../hardware/cips-config.md) - RPU, PMC, PS concepts
- [RAVE Peripherals](peripherals.md) - Peripheral details (EEPROM, TPM, eMMC, USB)
- [RAVE PCIe Configuration](pcie-config.md) - PL PCIe IP integration
- [CIPS Product Guide](https://docs.xilinx.com/r/en-US/pg352-cips) - CIPS IP documentation