# RAVE Board Documentation

> **For common hardware concepts**, see [Common Hardware Documentation](../hardware/index.md)
>
> This section contains comprehensive RAVE-specific documentation including hardware design, software services, installation guides, deployment, and testing.

## RAVE Board Overview

RAVE (Ryzen APU + Versal Edge) is a Mini-ITX embedded platform combining an AMD Ryzen processor with a Versal VE2302 FPGA device. The platform provides a complete standalone system optimized for edge computing, industrial, and automotive applications with balanced performance, power consumption, and cost.

The VE2302 is a Versal Edge-series device featuring GTYP transceivers for Gen3 PCIe connectivity and integrated LPDDR4 memory controllers. The platform connects the VE2302 to an on-board Ryzen R2314 or V2000-series processor via PCIe Gen3 x4, creating a hybrid processing architecture suitable for embedded and edge deployments.

The design implements PCIe and XDMA functionality using programmable logic IP blocks since the Edge-series devices do not include CPM hardened blocks. A 160-pin Samtec expansion connector provides access to additional GTYP transceivers and I/O signals, enabling application-specific daughtercards for networking, vision, and custom interfaces.

## RAVE-Specific Hardware Documentation

  - [RAVE - Hierarchy Overview](hierarchy.md) - RAVE block diagram and architecture

  - [RAVE - CIPS Configuration](cips-config.md) - VE2302 CIPS configuration

  - [RAVE - PCIe Configuration](pcie-config.md) - PL PCIe IP implementation (Gen3 x4)

  - [RAVE - XDMA Configuration](xdma-config.md) - XDMA PL IP setup (2 PFs)

  - [RAVE - Memory Resources](memory-resources.md) - 8-16GB LPDDR4 configuration

  - [RAVE - Memory Map](memory-map.md) - RAVE address mapping

  - [RAVE - NoC Configuration](noc-config.md) - RAVE NoC topology

  - [RAVE - Base Logic](base-logic.md) - RAVE PF0/PF1 implementation

  - [RAVE - Peripherals](peripherals.md) - Board-ID EEPROM, TPM, eMMC, USB, LEDs

  - [RAVE - Expansion I/O](expansion-io.md) - Samtec connector, daughtercard ecosystem

  - [RAVE - Clock Reset Module](clock-reset.md) - RAVE clock/reset configuration

  - [RAVE - Source File Overview](source-files.md) - RAVE build structure

## RAVE Board Variants

The RAVE family includes multiple hardware variants developed by Sapphire Technologies and AMD, each targeting specific market requirements and feature sets.

**board Variants:**
- **VPR-4616**: Initial board with 8GB LPDDR4
- **VPR-5050**: Enhanced processor variant
- **VPR-5050A**: Most feature-rich variant with 16GB LPDDR4, eMMC, USB 2.0 host

**Common Features:**
- VE2302 Versal device with PCIe Gen3 x4 connectivity
- 160-pin expansion connector for daughtercards
- Mini-ITX form factor

**Note:** For complete board specifications, variant differences, and feature lists, see the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) and related Sapphire product documentation.

## Key RAVE Features

### PL-Based PCIe and XDMA

The RAVE Board implements PCIe connectivity through the PCIe Versal IP instantiated in programmable logic. The VE2302 device uses GTYP Bank 103 for the x4 PCIe link operating at Gen3 speeds (8.0 GT/s), providing approximately 4 GB/s of raw bandwidth to the on-board Ryzen processor.

XDMA functionality comes from the XDMA PL IP supporting DMA operations through multiple channels. The XDMA provides efficient data transfer between host and device memory through AXI interfaces. The configuration uses 2 physical functions: PF0 (device ID 0x5710) for management and PF1 (device ID 0x5711) for user/DMA operations.

> **Note:** Legacy RAVE designs supported QDMA (Queue DMA) with a 512-queue architecture. The board has been migrated to XDMA for improved simplicity and compatibility with the VE2302 Embedded+ platform requirements.

The soft logic implementation for both PCIe and XDMA IP blocks represents a substantial portion of the available programmable logic. This resource usage must be factored into overall design planning when adding user applications and custom logic.

### LPDDR4 Memory

The RAVE Board includes 8 GB or 16 GB of LPDDR4 memory (depending on variant) organized as two channels with x32 configuration. The memory operates at 200 MHz providing 400 MT/s effective data rate through double-data-rate operation.

The LPDDR4 serves all memory requirements for the Versal device including firmware execution, inter-processor communication, user application data, and DMA buffers. Memory controller integration through the NoC enables access from the RPU, PMC, PCIe host, and programmable logic masters.

### Peripheral Integration

RAVE includes extensive peripheral integration supporting standalone embedded operation. A Board-ID EEPROM (M24C64) stores board identification and configuration data accessible via I2C at address 0x57. The TPM 2.0 security module (SLB9670) provides hardware-based cryptographic operations and secure key storage through an SPI interface.

The FTDI FT4232HQ USB-to-UART bridge enables multiple serial interfaces for debug and console access from the host system. Four status LEDs connected to MIO pins provide visual indication of system state and application status.

Enhanced variants (VPR-5050A) add eMMC storage via Versal MIO for persistent on-device data and a USB 2.0 host controller via Versal MIO for direct USB peripheral connectivity.

### Expansion I/O and Daughtercards

The 160-pin Samtec SEAM/SEAF expansion connector brings out GTYP Bank 104 transceivers (4 lanes), XPIO signals, and HDIO signals from the VE2302. This enables a daughtercard ecosystem including 1G Ethernet cards, 10G/25G Ethernet cards with dual SFP+ interfaces, and GMSL camera cards for vision applications.

## Technical Specifications Summary

**Versal Device:** VE2302 Versal Edge-series optimized for embedded applications

**PCIe Connectivity:** Gen3 x4 through GTYP Bank 103
- Device IDs: 0x5700 (PF0 management), 0x5701 (PF1 user/DMA)

**Memory:** LPDDR4 configuration (variant-dependent: 8GB or 16GB)

**Note:** For detailed memory configurations, processor variants, and complete technical specifications, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) and Sapphire product documentation.

## RAVE Target Applications

The RAVE Board is optimized for edge computing, industrial automation, and automotive applications. Target applications include:

- **Edge AI Inference**: Workloads requiring local processing at the edge
- **Industrial Automation**: Control systems, machine vision, and robotics
- **Automotive**: In-vehicle computing, ADAS development, and testing
- **Network Edge**: 5G edge computing with daughtercard networking options
- **Vision Systems**: GMSL camera integration for surveillance and inspection

The Mini-ITX form factor and embedded processor integration enable standalone deployment scenarios without requiring separate host systems.

## RAVE-Specific Software Documentation

For RAVE-specific software and deployment information, see:

- [AMI Software Services](../software/ami.md) - Adaptive Management Interface (common to all boards)

## RAVE-Specific AMR Installation

**How-to Install Prebuilt AMR Packages**

For installing prebuilt AMR packages on RAVE, see:

- [Install Prebuilt AMR Packages](../getting-started/install-prebuilt.md) - Download and install AMR packages for RAVE

**How-to Build an AMR Design for RAVE**

For building AMR from source for RAVE, see:

- [Build an AMR Design for RAVE](../getting-started/build_rave.md) - Complete build guide for RAVE

## References

- [Common Hardware Documentation](../hardware/index.md) - Shared Versal/CIPS/NoC concepts
- [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) - RAVE product information
- [AMR Release Information](../AMR-release-information.md) - Latest AMR release and download links