# AMR RAVE - Peripherals (RAVE-Specific)

> **For complete board specifications**, see [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html)
>
> This document describes AMR firmware/software interfaces to RAVE peripherals.

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## Overview

RAVE Boards include on-board peripherals for standalone embedded operation. This document focuses on the firmware and software interfaces used by AMR to access these peripherals.

**AMR-Managed Peripherals:**
- Board-ID EEPROM (I2C) - board identification
- TPM 2.0 (SPI) - Security operations
- Status LEDs (GPIO) - Status indication
- UART bridges - Console access

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## Board-ID EEPROM

The Board-ID EEPROM stores board identification and manufacturing information accessible via I2C.

**AMR Access:**
- **Firmware**: Via CIPS I2C peripheral (I2C address 0x57)
- **Host**: Via AMI commands
- **Use Case**: board identification for XRT/Vitis workflow

**EEPROM Content:**
- Board serial number
- Manufacturing information
- Platform UUID
- Interface UUID (BLP/ULP interface)
- Logic UUID (BLP functionality)

**Note:** For hardware specifications, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html).

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## TPM 2.0 Security Module

The TPM 2.0 module provides secure key storage and cryptographic operations accessible via SPI.

**AMR Access:**
- **Firmware**: Via CIPS SPI peripheral (PMC Bank 501)
- **Host**: Through firmware interface
- **Use Cases**: Secure boot, platform attestation, root of trust

**TPM Capabilities:**
- Secure key storage
- Cryptographic operations
- Platform attestation

**Note:** For hardware specifications, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html).

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## FTDI USB-to-UART Bridge

The FTDI bridge provides USB-to-serial conversion for console and debug access.

**Console Access:**
```bash
# Access Versal console (typically /dev/ttyUSB0)
minicom -D /dev/ttyUSB0

# List FTDI devices
lsusb | grep FTDI
```

**Typical Channel Configuration:**
- Channel A: Versal UART0 (console)
- Channel B: Versal UART1 (debug)

**Note:** For hardware specifications, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html).

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## Status LEDs

**Firmware Control:**
- **PMC MIO13**: Controlled by PMC (boot status)
- **LPD MIO0-2**: Controlled by RPU firmware via GPIO registers

**Use Cases:**
- Boot progress indication
- Error conditions
- User-defined status

**Note:** For LED placement and hardware details, refer to the [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html).

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## Board-specific Peripherals (VPR-5050A)

Some RAVE Board variants include additional peripherals:

**eMMC Storage (VPR-5050A only):**
- On-board persistent storage accessible via Versal MIO
- Used for boot images, configuration, logs

**USB 2.0 Host (VPR-5050A only):**
- USB 2.0 host controller via Versal MIO
- Supports USB storage, peripherals, debug interfaces

**Note:** For availability and specifications, refer to the specific board product page.

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## MIO Pin Configuration Summary

### PMC Bank 500 (OSPI)

| MIO Pin | Signal | Purpose |
|---------|--------|---------|
| 0 | CLK | OSPI clock |
| 1-7 | DQ0-DQ6 | OSPI data |
| 8 | DQS | Data strobe |
| 9 | DQ7 | OSPI data |
| 10 | CS_B | Chip select |
| 11 | CS1_B | Chip select 1 |
| 12 | RST | Reset |
| 13 | LED1 | Status LED |
| 16-17 | UART0 | RXD, TXD |
| 18-19 | I2C | SCL, SDA |
| 20-21 | UART1 | TXD, RXD |
| 24 | PCIe RST | PCIe reset |
| 25 | PCIe WAKE_B | PCIe wake |

### PMC Bank 501 (TPM, I2C1, SPI)

| MIO Pin | Signal | Purpose |
|---------|--------|---------|
| 26-31 | VCC Enables | Power control |
| 35-36 | I2C1 | SCL, SDA |
| 38-43 | SPI (TPM) | CLK, RST, SS_B, SO, SI |

### LPD Bank 502 (LEDs, I2C0)

| MIO Pin | Signal | Purpose |
|---------|--------|---------|
| 0-2 | LED2-4 | Status LEDs |
| 8-9 | ROM_REQ/GRT | ROM control |
| 10-11 | I2C0 | SCL, SDA |
| 24-25 | Monitors | 3V3_MON_P/N |

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## References

- [RAVE Expansion I/O](expansion-io.md) - Daughtercard interfaces
- [RAVE CIPS Configuration](cips-config.md) - MIO configuration details
- [Common Hardware](../hardware/index.md) - Shared Versal concepts
- [Sapphire RAVE1 EDGE+](https://www.amd.com/en/products/embedded/embedded-plus.html) - RAVE product info