# AMR V80 - Source File Overview
> **For common build concepts**, see [Common Source Files](../hardware/source-files.md)
>
> This document describes V80-specific build structure: alveo_v80 directory organization.
## Overview
The V80 hardware design files are organized under build_v80/amr_vivado_designs/alveo_v80/ with the v80_base design providing the base board implementation.
## Hardware Directory Tree
**V80 Hardware Source**
build_v80
└── amr_vivado_designs
├── README.md
├── LICENSE (MIT)
├── Jenkinsfile
├── alveo_v80
│ ├── scripts
│ │ └── gen_sdt.tcl
│ └── v80_base
│ ├── Makefile
│ ├── project (Generated: .xpr, .xsa)
│ ├── scripts
│ │ ├── main.tcl
│ │ └── config_bd.tcl
│ ├── xdc
│ │ ├── impl.xdc
│ │ └── impl.pins.xdc (364 lines, 64.8 KB)
│ └── ip
│ └── smbus_v1_1* (SystemVerilog custom IP)
│ ├── component.xml
│ ├── bd
│ │ └── bd.tcl
│ ├── hdl
│ │ └── smbus_v1_1_vl_rfs.sv
│ └── xgui
│ └── smbus_v1_1.tcl
└── emb_plus_ve2302 (VE2302 FPGA boards)
├── boards
│ ├── scripts
│ │ ├── gen_sdt.tcl
│ │ ├── gen_sdt_dfx.tcl
│ │ └── fix_dtsi.tcl
│ ├── ve2302_1gEth (1G Ethernet design)
│ ├── ve2302_10g_mrmac (10G Ethernet with MRMAC)
│ ├── ve2302_gmsl (GMSL pipeline)
│ ├── ve2302_xdma_gmsl (GMSL + XDMA/PCIe)
│ └── ve2302_xdma_base (DFX base design)
└── dfx (Dynamic Function eXchange)
├── common
│ └── bd
│ └── static_interface.tcl
├── bram_gpio
├── eth_1g
├── eth_10g
│ └── ip
│ └── MRMAC_AXI_MUX_V1_1 (Custom MRMAC MUX IP)
└── training
* : SMBus IP must be downloaded from
## build_v80
This is the top level directory containing the Vivado design sources for the AMR V80 hardware board.
### amr_vivado_designs
The amr_vivado_designs directory contains all hardware design files for multiple FPGA boards (Alveo V80 and VE2302). The repository supports Makefile-based builds with CI/CD integration via Jenkins.
#### alveo_v80
This directory contains the Alveo V80 FPGA design targeting the xcv80-lsva4737-2MHP-e-S part with Vivado 2025.2 tools.
##### v80_base
This is the V80 base platform design directory.
**Makefile** - Main build automation script supporting:
- `make xsa [JOBS=8]` - Generate Xilinx Support Archive (.xsa file)
- `make sdt` - Generate System Device Tree files using sdtgen
- `make all` - Complete build (XSA + SDT)
- `make clean` - Remove generated artifacts
- Default parallel synthesis jobs: 8 (configurable via JOBS parameter)
**project/** - Generated Vivado project directory containing:
- v80_base.xpr (Vivado project file)
- v80_base.xsa (Xilinx Support Archive - hardware definition)
###### scripts
- **main.tcl** - Main Vivado build script that:
- Creates the Vivado project
- Sets board part (xilinx.com:v80:part0:1.0)
- Loads XDC constraint files
- Updates IP catalog with custom IP repositories
- Sources config_bd.tcl to generate block design
- Runs synthesis and implementation
- Generates and validates XSA file
- Creates hardware documentation (README.hw)
- **config_bd.tcl** - Block design configuration script that instantiates and configures:
- **Versal CIPS** (CPM5 PCIe Gen5x8, RPU, PMC configuration)
- **AXI NoC instances** (3 total):
- axi_noc_cips: PCIe to PL routing (M00_AXI, M01_AXI) and memory controller connections
- axi_noc_mc_ddr4_0: Discrete DDR (4GB) controller interface
- axi_noc_mc_ddr4_1: DDR DIMM (32GB) controller interface
- **PF1 Hierarchy** (hierarchical block):
- SmartConnect: AXI interconnect (1 slave, 1 master)
- AXI GPIO: Test GPIO with loopback (default 0xF1)
- Processor System Reset: Reset synchronization
- **No management IP blocks** (GCQ, SMBus, UUID ROM, EEPROM) instantiated in base design
###### xdc
- **impl.pins.xdc** - Pin placement and I/O standard constraints (364 lines, 64.8 KB)
- DDR4 CH0 (Components): Address, data, control signals for memory controller 0
- Banks: 700, 701, 702
- IOSTANDARD: SSTL12 (address/control), POD12 (DM), DIFF_POD12 (DQS)
- VCCO: 1V2
- 72-bit data width (DQ[0-71], DM_n[0-8], DQS pairs)
- DDR4 CH1 (RDIMMs): Pin assignments for memory controller 1
- Banks: 703, 704, 705
- Similar signal structure with parity support
- **impl.xdc** - Implementation constraints (2.6 KB)
- SLR pblock definitions:
- pblock_SLR0: CLOCKREGION_X0Y0:CLOCKREGION_X12Y0, X0Y1:X9Y4
- pblock_SLR1: CLOCKREGION_X0Y5:CLOCKREGION_X9Y7
- pblock_SLR2: CLOCKREGION_X0Y8:CLOCKREGION_X9Y10, X0Y11:X8Y11
- Timing path exceptions and false paths
- NOC_NSU512 placement: LOC NOC_NSU512_X0Y0
- Reset synchronization false paths
###### ip
- **smbus_v1_1/** - Custom SMBus controller IP (SystemVerilog-based) - **NOT INSTANTIATED IN BASE DESIGN**
- **component.xml** - IP component definition (232 KB, 4598 lines)
- **bd/bd.tcl** - Block design for SMBus internal structure
- **hdl/smbus_v1_1_vl_rfs.sv** - SystemVerilog RTL implementation
- **xgui/smbus_v1_1.tcl** - GUI configuration interface
- *IMPORTANT*: This IP must be downloaded from the AMD member area () and placed in the ip/ directory for the design to build successfully
- *STATUS*: Available in IP repository but **not instantiated** in v80_base block design; M_AXI_LPD interface enabled but not connected (reserved for future SMBus instantiation)
#### emb_plus_ve2302
This directory contains multiple platform designs for the VE2302 Versal embedded FPGA targeting Vivado 2026.1 tools. It includes both flat (non-DFX) designs and Dynamic Function eXchange (DFX) capable designs.
##### boards
Multiple platform designs, each with similar structure (Makefile, scripts/, xdc/, and optional ip/):
- **ve2302_1gEth** - Dual-channel 1G Ethernet design using standard MAC
- **ve2302_10g_mrmac** - Dual 10G Ethernet design utilizing MRMAC (MultiRate MAC) hard blocks in Versal
- **ve2302_gmsl** - Versal GMSL (Gigabit Multimedia Serial Link) pipeline for video applications
- **ve2302_xdma_gmsl** - GMSL pipeline with XDMA/PCIe support
- **ve2302_xdma_base** - DFX-enabled base design with PCIe/XDMA, serves as base for reconfigurable modules
Each board build generates:
- XSA file (hardware definition)
- SDT files (system device tree)
- For DFX designs: partial PDI files and Debian packages
##### dfx (Dynamic Function eXchange)
Reconfigurable modules that can be dynamically loaded into the ve2302_xdma_base design:
- **common/bd/static_interface.tcl** - Defines the static (unchanging) interface between base design and reconfigurable partition
- **bram_gpio/** - BRAM storage + GPIO interface reconfigurable module
- **eth_1g/** - Single 1G Ethernet reconfigurable module
- **eth_10g/** - Single 10G Ethernet with MRMAC reconfigurable module
- Contains custom **MRMAC_AXI_MUX_V1_1** IP (38 KB component.xml)
- Custom Verilog modules: mrmac_10g_mux.v, axis_dwidth_converter_rx/, axis_dwidth_converter_tx/
- **training/** - Reference training reconfigurable module
DFX build outputs:
- Base XSA: ve2302_xdma_base.xsa
- Module XSAs: ve2302_xdma_base_{module}.xsa
- Partial PDIs: {module}_partial.pdi
- Debian packages: amr-{module}-dma-test-ve2302_2.0.deb
##### SDT (System Device Tree) Generation
- **gen_sdt.tcl** - Generates device tree for flat designs
- Uses sdtgen utility with board-specific device tree (versal-emb-plus-ve2302-reva)
- Outputs to project_sdt/ directory
- **gen_sdt_dfx.tcl** - Generates device tree for DFX designs with multiple XSA file support
- **fix_dtsi.tcl** - Post-processing script for device tree files
### CI/CD Integration
**Jenkinsfile** - Jenkins pipeline configuration providing:
- Multi-host deployment support
- Commit ID tracking (source + submodules)
- Remote build invocation via LSF (Load Sharing Facility)
- XSA artifact deployment
- Debian package deployment
- Build success symlink management
- Branch-specific deployment logic