# AMR common Hardware Design 

This section contains hardware design documentation **common to all AMR boards** (V80, RAVE). For board-specific details, see the individual board documentation.

## Board Documentation

  - [V80 Hardware Design](../V80/index.md) - Alveo V80 (CPM5, HBM)

  - [RAVE Hardware Design](../RAVE/index.md) - Embedded+ VE2302 (PL PCIe, LPDDR4)

## Common Hardware Documentation

  - [Board Comparison](../overview/amr-overview.md#amroverview-supportedboards) - V80 vs RAVE comparison and selection guide

  - [Versal Architecture Overview](hierarchy.md) - Common Versal concepts (CIPS, PL, NoC)

  - [CIPS Common Configuration](cips-config.md) - RPU, PMC, and PS peripheral concepts

  - [Base Design Philosophy](base-logic.md) - Minimal design, software GCQ, firmware-based management

  - [Memory Architecture Concepts](memory-resources.md) - DDR, memory controllers, general concepts

  - [Address Mapping Concepts](memory-map.md) - PCIe to AXI address translation

  - [NoC Interconnect Overview](noc-config.md) - NoC concepts (NMU, NSU, NPS, performance)

  - [Clock and Reset Concepts](clock-reset.md) - CIPS clocks, reset synchronization

  - [Build System Overview](source-files.md) - Vivado build structure and flow

## Key Common Design Principles

### Minimal Base Design
All AMR boards follow a minimal base design philosophy:
- No management IP blocks in PL (no GCQ hardware, UUID ROM, EEPROM controllers)
- Firmware-based management using RPU (R5 processors)
- Software GCQ implementation using shared DDR memory
- Expansion points available (M_AXI_LPD, address space, interrupts)

### Boards-Agnostic Concepts
The following concepts are shared across all boards:
- Versal CIPS architecture (RPU, PMC, PS)
- NoC interconnect fundamentals
- Memory controller architecture
- Boot and configuration flow
- 2 Physical Functions (PF0 management, PF1 user/DMA)
- QDMA for DMA transfers (different implementations)

### Board-Specific Implementations
See individual board documentation for:
- **V80**: CPM5 hardened PCIe, HBM memory, Gen5x8 configuration
- **RAVE**: PL-based PCIe IP, LPDDR4 memory, expansion I/O, peripherals