# AMR - NoC Interconnect Overview (Common)

> **For Board-specific NoC configurations**, see:
> - [V80 NoC Configuration](../V80/noc-config.md) - CPM5 hardened NoC, HBM connections
> - [RAVE NoC Configuration](../RAVE/noc-config.md) - PL PCIe NMU_512, LPDDR4 only

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## Network-On-Chip (NoC) Overview

AMD Versal™ devices use a programmable NoC interconnect based on AXI-4 for high-bandwidth communication throughout the device. The NoC simplifies timing requirements when routing across long distances, multiple SLRs, or connecting to opposite sides of the die.

The NoC provides a high-bandwidth interconnect based on the AXI-4 protocol, enabling efficient data movement throughout the Versal device. The NoC connects CIPS blocks to programmable logic regions and to memory controllers, handling address decoding, routing, and quality-of-service arbitration. The routing is programmable through configuration of the AXI NoC IP, allowing designs to specify bandwidth requirements and connectivity patterns that the NoC compiler optimizes. The NoC spans multiple super logic regions (SLRs) through vertical NoC (VNoC) channels and horizontal NoC (HNoC) channels that interconnect across the device.

Board-specific NoC topologies reflect the different PCIe and memory architectures. Some boards feature hardened PCIe blocks with integrated NoC connections and may include HBM NoC ports for high-bandwidth memory access. Other boards route PCIe traffic through programmable logic NMU interfaces and focus on DDR memory connectivity without HBM integration.

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## NoC Components

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### NoC Master Units (NMU)

NMUs connect AXI masters to the NoC. Three types exist in Versal:

#### NMU_512 (PL)

The NMU_512 provides full-featured NoC master connectivity for programmable logic IP blocks. The data width is configurable from 32 to 512 bits for AXI4 memory-mapped interfaces or from 128 to 512 bits for AXI4-Stream interfaces. This flexibility accommodates various IP block requirements from narrow control interfaces to wide data paths. PL-based PCIe IP blocks typically use NMU_512 interfaces to connect to the NoC, with the wider widths supporting high-bandwidth DMA operations. The NMU_512 units connect to the Vertical NoC channels for routing throughout the device.

[NMU_512 Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/NMU512-PL)

#### NMU_128 (Low Latency)

The NMU_128 is optimized for hardened blocks in the CIPS including CPM, PMC, and RPU connections to the NoC. The data width is fixed at 128 bits, matching the native interface widths of these hardened blocks. This specialized unit does not support AXI4-Stream protocol, focusing exclusively on memory-mapped transfers. The optimization for hardened blocks provides lower latency compared to NMU_512, benefiting latency-sensitive operations such as processor memory access and PCIe transactions through hardened controllers.

[NMU_128 Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/NMU128-Low-Latency)

#### HBM_NMU (V80 Only)

The HBM_NMU provides direct HBM access from programmable logic when HBM is present in the device. The data width is configurable from 32 to 256 bits depending on the application bandwidth requirements. These units enable PL logic to saturate HBM memory bandwidth through parallel access to multiple HBM controllers. The HBM_NMU units are distributed across the top of SLR2 to facilitate routing to the HBM stacks. This unit type is available only on Versal HBM-series devices; Edge-series devices do not include HBM and therefore do not provide HBM_NMU interfaces.

[HBM_NMU Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/HBM_NMU)

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### NoC Slave Units (NSU)

NSUs connect the NoC to AXI slaves. Four types exist:

#### NSU_512 (PL)

**Full-featured NoC slave for PL connections:**
- Data width: 32-512 bits (AXI4-MM) or 128-512 bits (AXI4-Stream)
- Use case: NoC to PL AXI slaves
- Location: Connects from Vertical NoC

[NSU_512 Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/NSU512-PL)

#### NSU_128 (Low Latency)

**Optimized for hardened blocks:**
- Data width: Fixed 128 bits
- Use case: NoC to CIPS peripherals
- No AXI4-Stream support

[NSU_128 Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/NSU128-Low-Latency)

#### DDRMC_NSU

**Direct NoC to DDR memory controller:**
- Partial NSU functionality
- Converts NoC packets directly to memory controller domain
- No AXI protocol conversion overhead
- Used by all AMR boards for DDR access

[DDRMC_NSU Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/DDRMC-NSU)

#### HBM_NSU (V80 Only)

**Direct NoC to HBM controller:**
- Two NSU per HBM pseudo channel
- Converts NoC packets to HBM controller domain
- **V80 specific** - RAVE has no HBM

[HBM_NSU Documentation](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/HBM_NSU)

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### NoC Packet Switches (NPS)

**NPS route traffic between NMUs and NSUs:**
- Located at intersections of VNoC and HNoC
- Programmable routing determined by NoC compiler
- QoS arbitration at each switch

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## NoC Physical Architecture

### Horizontal NoC (HNoC)

**Each SLR contains 2 HNoCs:**
- **Bottom HNoC**: Connects to CIPS and DDR controllers
- **Top HNoC**: Optimized for HBM connections (V80 only, in SLR2)
- Span entire width of SLR
- Connect to VNoCs

### Vertical NoC (VNoC)

**Each SLR contains VNoCs:**
- Span entire height of SLR
- Connect to adjacent SLRs
- Route traffic between HNoCs and across SLRs

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## AXI NoC IP

### Common Usage

All AMR boards use **AXI NoC IP** (xilinx.com:ip:axi_noc) to configure NoC connections:

The AXI NoC IP provides comprehensive configuration capabilities for NoC connectivity. The IP configures AXI Master and Slave interfaces that connect programmable logic to the NoC fabric. INI (Inter-NoC Interconnect) connections link multiple NoC instances together enabling traffic to traverse between them. Memory controller instantiation occurs within the NoC IP configuration, with support for DDRMC and HBM controllers depending on the device capabilities. Quality of Service (QoS) and bandwidth specification parameters guide the NoC compiler in resource allocation and routing decisions. Address remapping capabilities enable translation between different address domains. Clock domain crossing management handles asynchronous interfaces with appropriate synchronization logic.

The typical instantiation pattern includes a main NoC instance (commonly named "axi_noc_cips") that handles primary connectivity between CIPS, PCIe, and programmable logic. Additional NoC instances are dedicated to memory controller integration, providing INI interfaces for the main NoC to access memory.

board differences appear in the number and configuration of NoC instances. boards with multiple memory types may use three or more NoC instances to manage the various memory controllers (discrete DDR, DIMM, HBM). boards with simpler memory architectures may use one or two NoC instances focused on a single memory type such as LPDDR4.

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## Quality of Service (QoS)

### Traffic Classes

**Three traffic classes available:**

| Class | Priority | Use Case |
|-------|----------|----------|
| **Low Latency** | Highest | CPU to DDR transactions |
| **Isochronous** | Medium | Real-time deadlines |
| **Best Effort** | Lowest | Bulk transfers, not time-critical |

**AMR Usage:** All boards use **Best Effort** for most connections.

### Bandwidth Requirements

Quality of Service specifications include bandwidth requirements for both read and write directions measured in MB/s, along with average burst size parameters that indicate typical transaction sizes. The NoC compiler uses these QoS specifications to determine optimal routing paths through the NoC fabric and to allocate NoC resources such as NMU, NSU, and NPS units. The compiler attempts to satisfy all bandwidth requirements while minimizing resource usage and avoiding congestion in the NoC infrastructure.

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## Common NoC Connection Patterns

### PCIe to Memory

All boards route PCIe DMA traffic to memory through a consistent pattern regardless of the specific PCIe implementation. The path begins at the PCIe block (whether hardened or in PL), connects to a NoC Master Unit (NMU), routes through the NoC to an Inter-NoC Interconnect (INI) interface, and terminates at the memory controller's DDRMC_NSU which converts to the memory controller domain. The specific NMU type varies by board, with hardened PCIe blocks using NMU_128 for optimized low-latency paths and PL-based PCIe IP using NMU_512 for soft logic connectivity.

### RPU to Memory

All boards route RPU firmware access to DDR memory through the LPD_AXI_NOC_0 interface. The path begins at the RPU within CIPS, exits through the LPD_AXI_NOC_0 port (a 128-bit interface operating at 800MHz), routes through the NoC fabric, and terminates at the DDRMC_NSU interface of the memory controller. This path carries firmware instruction fetches, data reads and writes, and software GCQ buffer access. The 128-bit interface width and 800 MHz operating frequency provide adequate bandwidth for typical firmware memory access patterns.

### PMC to Memory

All boards route PMC access to DDR memory through the PMC_NOC_AXI_0 interface during boot and configuration operations. The path begins at the PMC within CIPS, exits through the PMC_NOC_AXI_0 port (a 128-bit interface operating at 400MHz), routes through the NoC fabric, and terminates at the DDRMC_NSU interface. The PMC uses this path during boot to initialize memory, load firmware code and data structures, and perform configuration activities. The 400 MHz operating frequency is adequate for boot-time memory access where bandwidth requirements are moderate compared to runtime DMA operations.

### PCIe to PL

All boards route PCIe traffic to programmable logic peripherals through NoC master interfaces that exit the NoC and enter the PL address space. The PCIe traffic routes through the NoC fabric to AXI Master interfaces, typically designated as M00_AXI and M01_AXI, which connect to programmable logic hierarchical blocks or individual peripherals. The common pattern allocates M00_AXI for PF0 management address space access and M01_AXI for PF1 user and test address space access. This separation enables independent address decode and access control for management versus user functions.

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## NoC Performance Tuning

### Bandwidth Optimization

Common tuning approaches for NoC performance optimization include adjusting QoS bandwidth requirements to accurately reflect actual traffic patterns, optimizing memory controller address mapping to maximize row buffer hits and minimize bank conflicts, balancing traffic across available NoC resources to avoid congestion hotspots, and utilizing multiple memory controller ports when bandwidth demands justify parallel access paths. These techniques work together to maximize overall system throughput while meeting latency requirements for latency-sensitive operations.

### Memory Controller Tuning

**DDRMC Optimization:**
- Address mapping (row/column/bank interleaving)
- Refresh configuration
- Port arbitration

**Board-specific:** See V80 or RAVE NoC configuration for specific tuning.

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## Additional Resources

**NoC Documentation:**
- [Versal Programmable NoC Overview](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/Versal-Programmable-NoC-Overview)
- [Configuring AXI NoC](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/Configuring-the-AXI-NoC)
- [NoC Performance Tuning](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/NoC-Performance-Tuning)

**Performance References:**
- [Physical Link Raw Bandwidth](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/Physical-Link-Raw-Bandwidth)
- [Packetization Overhead](https://docs.xilinx.com/r/en-US/pg313-network-on-chip/Packetization-Overhead)

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## Board-specific NoC Topologies

For complete NoC configurations including connection diagrams, routing, and QoS settings:

### V80 NoC Topology
[V80 NoC Configuration](../V80/noc-config.md)

**V80-Specific NoC Features:**
- CPM5 hardened connection (NMU_128)
- 3 AXI NoC instances
- HBM controller connections (32 ports)
- DDR DIMM controller
- Complex topology with multiple memory types

### RAVE NoC Topology
[RAVE NoC Configuration](../RAVE/noc-config.md)

**RAVE-Specific NoC Features:**
- PL PCIe IP connection (NMU_512)
- 1-2 AXI NoC instances
- LPDDR4 controller only
- Simpler topology (no HBM, no DIMM)