# AMR V80 - Source File Overview

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## Hardware Directory Tree

**Hardware Source**

    └── amr_vivado_designs
    └── alveo_v80
    └── boards
    ├── scripts
    │   └── gen_sdt.tcl
    └── v80_base
    ├── ip
    │   └── smbus_v1_1*
    │       ├── src
    │       │   └── ...
    │       ├── xgui
    │       │   ├── smbus_v1_1.tcl
    │       │   └── smbus_v1_1_v1_0.tcl
    │       └── component.xml
    ├── Makefile
    ├── scripts
    │   ├── config_bd.tcl
    │   └── main.tcl
    └── xdc
    ├── impl.pins.xdc
    └── impl.xdc

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## amr

This is the top level directory containing the source files for creating the AMR design and the build script. When executed, the build.sh script builds the hardware design, firmware, and final PDI.

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### hw

The hw directory contains the files necessary to build the hardware design.

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##### build.sh

This is the main build shell. Executing this shell will launch Vivado<sup>TM</sup>, build the AMR hardware design, compile the AMC firmware, and generate the PDI files. This is indicated by the asterisk in the Hardware Directory Tree above.

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##### PDI Gen - This is used in the build.sh to combine the FW amc.elf with the HW PDI.

- output: build_amc/amr_ospi_fpt.bin
- fpt\_pdi\_gen.py - This file is used in the build.sh to create the final FPT PDI

  - output: amr_ospi.bin and amr_ospi_fpt.bin

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##### src

- **bd** - This is the Block Design generation directory which contains the TCL file necessary to build the AMD Vivado™ AMR design.

  - create\_bd\_design.tcl - This TCL file is used by Vivado to create the base AMR design. Since the GTs are not used in this design, the interface ports have been commented out. The user may uncomment them as required for their design.
- **build\_design.tcl** - This script uses Vivado to create the XSA and run synthesis and implementation.
- **constraints** - This directory contains the constraints required for Vivado implementation to generate a PDI.

  - impl.pins.xdc - This file contains the top level I/O pin names, locations, and IO standards for the DDR, DIMM, GTYPs, GTMs, and clocks.

    - *Note*: Since the GTs are not used in the base V80 design, these pins have been commented out.

  impl.xdc - This file defines strictly enforced pblocks for each SLR. A strictly enforced pblock does not allow cells to be moved outside pblock boundaries. The base logic is assigned to SLR0, while user logic can be assigned to SLR0, SLR1, and SLR2 as needed.

  The NMU for the PCIe Management SmartConnect (pcie\_slr0\_mgmt\_sc) is LOC’d to keep the base logic resources close to the CIPS in SLR0.

  - opt.post.tcl - This file turns on bitstream compression and enables NPI DMA mode to accelerate device download. It also disables BUFG insertion in placement to prevent clock changes.
  - place.pre.tcl - The PCIe Management PDI Reset logic currently is not used in AMR, but it was added for future growth. Currently, the settings in this file connect the reset to a PMC interrupt. The response to this interrupt has not been defined.
  - write\_device\_image.pre.tcl - This file generates the UUID for the AMR design which is stored in the UUID of the base logic.
  - **create\_design.tcl** - This file is used by Vivado to create the project, create the BD, add the constraint files, and set the processing order for creating the AMR design.
  - **iprepo** - This directory contains all the additional IP necessary to build the AMR design that is not included in the Vivado released SW.

    - smbus\_v1\_1 - This IP is used by the v80 to communicate with server board management controller.