PCIe

The PCIe debug core is an optional addition to the Versal CPM PCIe functionality, or an optional addition to the Versal Soft PCIe core. When included, PCIe debug will track transitions on the Link Training and Status State Machine (LTSSM), and make that trace and associated statistics available though properties on the PCIe object.

• Details
  • Core Details
  • LTSSM State Visit Tracking
  • LTSSM State Transition Tracking
  • LTSSM Trace
• References
  • chipscopy.PCIe