SysMon¶
The System Monitor block in versal is a redesign from prior Xilinx architectures. Some of the key concepts are the same but the specifics of the implementation are different in Versal. The basic features are carried forward:
Device temperature measurement
Supply voltage measurements
Bank and VCCINT measurements
Auxiliary channel measurements through MIO
VP_VN (low resistance) measurement via dedicated bump
Averaging, measurement mode control
Over Temp/Threshold alarms and actions
The typical use case is to configure the SysMon block in the Control Interfaces and Processing Subsystem (CIPS) in the open design in Vivado. There are more advanced APIs that allow for dynamic reconfiguration of the SysMon block, but the user assumes responsibility for all outcomes when using these APIs.
