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axivdma
Vitis Drivers API Documentation
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axivdma
Vitis Drivers API Documentation
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Macros | |
| #define | XAXIVDMA_MISMATCH_ERROR 0x80000010 |
| Frame/Line Mismatch Error This is a typical DMA Internal Error, which on detection doesnt require a reset (as opposed to other errors). More... | |
| #define | XAxiVdma_ReadReg(BaseAddress, RegOffset) XAxiVdma_In32((BaseAddress) + (RegOffset)) |
| Read the given register. More... | |
| #define | XAxiVdma_WriteReg(BaseAddress, RegOffset, Data) XAxiVdma_Out32((BaseAddress) + (RegOffset), (Data)) |
| Write the given register. More... | |
Buffer Descriptor Alignment | |
| #define | XAXIVDMA_BD_MINIMUM_ALIGNMENT 0x20 |
| Minimum byte alignment requirement for descriptors. More... | |
| #define | XAXIVDMA_BD_MINIMUM_ALIGNMENT_WD 0x8 |
| Minimum word alignment requirement for descriptors. More... | |
| #define | XAXIVDMA_MAX_FRAMESTORE 32 |
| Maximum number of the frame store. More... | |
| #define | XAXIVDMA_MAX_FRAMESTORE_64 16 |
| Maximum # of the frame store for 64 bit. More... | |
Maximum transfer length | |
This is determined by hardware | |
| #define | XAXIVDMA_MAX_VSIZE 0x1FFF /* Max vertical size, 8K */ |
| #define | XAXIVDMA_MAX_HSIZE 0xFFFF /* Max horizontal size, 64K */ |
| #define | XAXIVDMA_MAX_STRIDE 0xFFFF /* Max stride size, 64K */ |
| #define | XAXIVDMA_FRMDLY_MAX 0xF |
| Maximum frame delay. More... | |
Device registers | |
Register sets on TX (Read) and RX (Write) channels are identical The version register is shared by both channels | |
| #define | XAXIVDMA_TX_OFFSET 0x00000000 |
| TX channel registers base. More... | |
| #define | XAXIVDMA_RX_OFFSET 0x00000030 |
| RX channel registers base. More... | |
| #define | XAXIVDMA_PARKPTR_OFFSET 0x00000028 |
| Park Pointer Register. More... | |
| #define | XAXIVDMA_VERSION_OFFSET 0x0000002C |
| Version register. More... | |
| #define | XAXIVDMA_CR_OFFSET 0x00000000 |
| Channel control. More... | |
| #define | XAXIVDMA_SR_OFFSET 0x00000004 |
| Status. More... | |
| #define | XAXIVDMA_CDESC_OFFSET 0x00000008 |
| Current descriptor pointer. More... | |
| #define | XAXIVDMA_TDESC_OFFSET 0x00000010 |
| Tail descriptor pointer. More... | |
| #define | XAXIVDMA_HI_FRMBUF_OFFSET 0x00000014 |
| 32 FrameBuf Sel More... | |
| #define | XAXIVDMA_FRMSTORE_OFFSET 0x00000018 |
| Frame Store. More... | |
| #define | XAXIVDMA_BUFTHRES_OFFSET 0x0000001C |
| Line Buffer Thres. More... | |
| #define | XAXIVDMA_MM2S_ADDR_OFFSET 0x00000050 |
| MM2S channel Addr. More... | |
| #define | XAXIVDMA_S2MM_ADDR_OFFSET 0x000000A0 |
| S2MM channel Addr. More... | |
| #define | XAXIVDMA_VFLIP_OFFSET 0x000000EC |
| Enable Vertical Flip Register. More... | |
| #define | XAXIVDMA_S2MM_DMA_IRQ_MASK_OFFSET 0x0000003C |
| S2MM Err IRQ Mask. More... | |
Start Addresses Register Array for a Channel | |
Base offset is set in each channel This set of registers are write only, they can be read when C_ENABLE_VIDPRMTR_READS is 1. | |
| #define | XAXIVDMA_VSIZE_OFFSET 0x00000000 |
| Vertical size. More... | |
| #define | XAXIVDMA_HSIZE_OFFSET 0x00000004 |
| Horizontal size. More... | |
| #define | XAXIVDMA_STRD_FRMDLY_OFFSET 0x00000008 |
| Horizontal size. More... | |
| #define | XAXIVDMA_START_ADDR_OFFSET 0x0000000C |
| Start of address. More... | |
| #define | XAXIVDMA_START_ADDR_LEN 0x00000004 |
| Each entry is 4 bytes. More... | |
| #define | XAXIVDMA_START_ADDR_MSB_OFFSET 0x00000010 |
| Start of address. More... | |
Bitmasks of the XAXIVDMA_CR_OFFSET register | |
| #define | XAXIVDMA_CR_RUNSTOP_MASK 0x00000001 |
| Start/stop DMA channel. More... | |
| #define | XAXIVDMA_CR_TAIL_EN_MASK 0x00000002 |
| Tail ptr enable or Park. More... | |
| #define | XAXIVDMA_CR_RESET_MASK 0x00000004 |
| Reset channel. More... | |
| #define | XAXIVDMA_CR_SYNC_EN_MASK 0x00000008 |
| Gen-lock enable. More... | |
| #define | XAXIVDMA_CR_FRMCNT_EN_MASK 0x00000010 |
| Frame count enable. More... | |
| #define | XAXIVDMA_CR_FSYNC_SRC_MASK 0x00000060 |
| Fsync Source Select. More... | |
| #define | XAXIVDMA_CR_GENLCK_SRC_MASK 0x00000080 |
| Genlock Source Select. More... | |
| #define | XAXIVDMA_CR_RD_PTR_MASK 0x00000F00 |
| Read pointer number. More... | |
| #define | XAXIVDMA_CR_GENLCK_RPT_MASK 0x00008000 |
| GenLock Repeat. More... | |
| #define | XAXIVDMA_VFLIP_EN_MASK 0x00000001 |
| Vertical flip enable. More... | |
| #define | XAXIVDMA_CR_RD_PTR_SHIFT 8 |
| Shift for read pointer number. More... | |
Bitmasks of the XAXIVDMA_SR_OFFSET register | |
This register reports status of a DMA channel, including run/stop/idle state, errors, and interrupts | |
| #define | XAXIVDMA_SR_HALTED_MASK 0x00000001 |
| DMA channel halted. More... | |
| #define | XAXIVDMA_SR_IDLE_MASK 0x00000002 |
| DMA channel idle. More... | |
| #define | XAXIVDMA_SR_ERR_INTERNAL_MASK 0x00000010 |
| Datamover internal err. More... | |
| #define | XAXIVDMA_SR_ERR_SLAVE_MASK 0x00000020 |
| Datamover slave err. More... | |
| #define | XAXIVDMA_SR_ERR_DECODE_MASK 0x00000040 |
| Datamover decode err. More... | |
| #define | XAXIVDMA_SR_ERR_FSZ_LESS_MASK 0x00000080 |
| FSize Less Mismatch err. More... | |
| #define | XAXIVDMA_SR_ERR_LSZ_LESS_MASK 0x00000100 |
| LSize Less Mismatch err. More... | |
| #define | XAXIVDMA_SR_ERR_SG_SLV_MASK 0x00000200 |
| SG slave err. More... | |
| #define | XAXIVDMA_SR_ERR_SG_DEC_MASK 0x00000400 |
| SG decode err. More... | |
| #define | XAXIVDMA_SR_ERR_FSZ_MORE_MASK 0x00000800 |
| FSize More Mismatch err. More... | |
| #define | XAXIVDMA_SR_ERR_ALL_MASK 0x00000FF0 |
| All errors. More... | |
Bitmask for interrupts | |
These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register | |
| #define | XAXIVDMA_IXR_FRMCNT_MASK 0x00001000 |
| Frame count intr. More... | |
| #define | XAXIVDMA_IXR_DELAYCNT_MASK 0x00002000 |
| Delay interrupt. More... | |
| #define | XAXIVDMA_IXR_ERROR_MASK 0x00004000 |
| Error interrupt. More... | |
| #define | XAXIVDMA_IXR_COMPLETION_MASK 0x00003000 |
| Completion interrupts. More... | |
| #define | XAXIVDMA_IXR_ALL_MASK 0x00007000 |
| All interrupts. More... | |
Bitmask and shift for delay and coalesce | |
These masks are shared by the XAXIVDMA_CR_OFFSET register and the XAXIVDMA_SR_OFFSET register | |
| #define | XAXIVDMA_DELAY_MASK 0xFF000000 |
| Delay timeout counter. More... | |
| #define | XAXIVDMA_FRMCNT_MASK 0x00FF0000 |
| Frame counter. More... | |
| #define | XAXIVDMA_REGINDEX_MASK 0x00000001 |
| Register Index. More... | |
| #define | XAXIVDMA_DELAY_SHIFT 24 |
| #define | XAXIVDMA_FRMCNT_SHIFT 16 |
Bitmask for the XAXIVDMA_CDESC_OFFSET register | |
| #define | XAXIVDMA_CDESC_CURBD_MASK 0xFFFFFFE0 |
| BD now working on. More... | |
Bitmask for XAXIVDMA_TDESC_OFFSET register | |
| #define | XAXIVDMA_TDESC_CURBD_MASK 0xFFFFFFE0 |
| BD to stop on. More... | |
Bitmask for XAXIVDMA_FRMSTORE_OFFSET register | |
| #define | XAXIVDMA_FRMSTORE_MASK 0x0000003F |
Bitmask for XAXIVDMA_PARKPTR_OFFSET register | |
| #define | XAXIVDMA_PARKPTR_READREF_MASK 0x0000001F |
| Read frame to park on. More... | |
| #define | XAXIVDMA_PARKPTR_WRTREF_MASK 0x00001F00 |
| Write frame to park on. More... | |
| #define | XAXIVDMA_PARKPTR_READSTR_MASK 0x001F0000 |
| Current read frame. More... | |
| #define | XAXIVDMA_PARKPTR_WRTSTR_MASK 0x1F000000 |
| Current write frame. More... | |
| #define | XAXIVDMA_READREF_SHIFT 0 |
| #define | XAXIVDMA_WRTREF_SHIFT 8 |
| #define | XAXIVDMA_READSTR_SHIFT 16 |
| #define | XAXIVDMA_WRTSTR_SHIFT 24 |
| #define | XAXIVDMA_FRM_MAX 0xF |
| At most 16 frames. More... | |
Bitmask for XAXIVDMA_VERSION_OFFSET register | |
| #define | XAXIVDMA_VERSION_MAJOR_MASK 0xF0000000 |
| Major version. More... | |
| #define | XAXIVDMA_VERSION_MINOR_MASK 0x0FF00000 |
| Minor version. More... | |
| #define | XAXIVDMA_VERSION_REV_MASK 0x000F0000 |
| Revision letter. More... | |
| #define | XAXIVDMA_VERSION_MAJOR_SHIFT 28 |
| #define | XAXIVDMA_VERSION_MINOR_SHIFT 20 |
Bitmask for XAXIVDMA_S2MM_IRQ_MASK_OFFSET register | |
| #define | XAXIVDMA_S2MM_IRQ_FSZLESS_SOF_ERLY_MASK 0x00000001 |
| Masks S2MM IRQ FSize Less/SOF Early Error. More... | |
| #define | XAXIVDMA_S2MM_IRQ_LSZLESS_EOL_ERLY_MASK 0x00000002 |
| Masks S2MM IRQ LSize Less/EOL Early Error. More... | |
| #define | XAXIVDMA_S2MM_IRQ_FSZMORE_SOF_LATE_MASK 0x00000004 |
| Masks S2MM IRQ FSize More/SOF Late Error. More... | |
| #define | XAXIVDMA_S2MM_IRQ_LSZMORE_EOL_LATE_MASK 0x00000008 |
| Masks S2MM IRQ LSize More/EOL Late Error. More... | |
| #define | XAXIVDMA_S2MM_IRQ_ERR_ALL_MASK 0x0000000F |
| Masks all S2MM IRQ Errors. More... | |
Frame Delay shared by start address registers and BDs | |
| #define | XAXIVDMA_VSIZE_MASK 0x00001FFF |
| Vertical size. More... | |
| #define | XAXIVDMA_HSIZE_MASK 0x0000FFFF |
| Horizontal size. More... | |
| #define | XAXIVDMA_STRIDE_MASK 0x0000FFFF |
| Stride size. More... | |
| #define | XAXIVDMA_FRMDLY_MASK 0x0F000000 |
| Frame delay. More... | |
| #define | XAXIVDMA_FRMDLY_SHIFT 24 |
| Shift for frame delay. More... | |
Buffer Descriptor offsets | |
| #define | XAXIVDMA_BD_NDESC_OFFSET 0x00 |
| Next descriptor pointer. More... | |
| #define | XAXIVDMA_BD_START_ADDR_OFFSET 0x08 |
| Start address. More... | |
| #define | XAXIVDMA_BD_VSIZE_OFFSET 0x10 |
| Vertical size. More... | |
| #define | XAXIVDMA_BD_HSIZE_OFFSET 0x14 |
| Horizontal size. More... | |
| #define | XAXIVDMA_BD_STRIDE_OFFSET 0x18 |
| Stride size. More... | |
| #define | XAXIVDMA_BD_NUM_WORDS 7 |
| Total number of words for one BD. More... | |
| #define | XAXIVDMA_BD_HW_NUM_BYTES 28 |
| Number of bytes hw used. More... | |
| #define | XAXIVDMA_BD_BYTES_TO_CLEAR 20 |
| Skip next ptr when clearing. More... | |