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dsi
Vitis Drivers API Documentation
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dsi
Vitis Drivers API Documentation
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Macros | |
| #define | XDSI_MAX_LANES 4 |
| Max Lanes supported by DSI. More... | |
Device registers | |
Register sets of MIPI DSI Tx | |
| #define | XDSI_CCR_OFFSET 0x00000000 |
| Core Configuration Register Offset. More... | |
| #define | XDSI_PCR_OFFSET 0x00000004 |
| Protocol Configuration Register Offset. More... | |
| #define | XDSI_GIER_OFFSET 0x00000020 |
| Global Interrupt Register Offset. More... | |
| #define | XDSI_ISR_OFFSET 0x00000024 |
| Interrupt Status Register. More... | |
| #define | XDSI_IER_OFFSET 0x00000028 |
| Interrupt Enable Register. More... | |
| #define | XDSI_STATUS_OFFSET 0x0000002C |
| Status Register. More... | |
| #define | XDSI_COMMAND_OFFSET 0x00000030 |
| Packet Entry to command Queue. More... | |
| #define | XDSI_DATA_OFFSET 0x00000034 |
| Packet Data to data Queue. More... | |
| #define | XDSI_TIME1_OFFSET 0x00000050 |
| Time 1 Offset. More... | |
| #define | XDSI_TIME2_OFFSET 0x00000054 |
| Time 2 Offset. More... | |
| #define | XDSI_TIME3_OFFSET 0x00000058 |
| Time 3 Offset. More... | |
| #define | XDSI_TIME4_OFFSET 0x0000005C |
| Time 4 Offset. More... | |
| #define | XDSI_LTIME_OFFSET 0x00000060 |
| Total Line Timing Offset. More... | |
| #define | XDSI_BLLP_TIME_OFFSET 0x00000064 |
| BLLP Time duration Offset. More... | |
| #define | XDSI_TIME5_OFFSET 0x0000006C |
| Time 5 Offset. More... | |
Core configuration register masks and shifts | |
This register is used for the enabling/disabling and resetting the core of DSI Tx Controller | |
| #define | XDSI_CCR_RESET_CMD_FIFO_MASK 0x00000020 |
| Command FIFO Reset bit Mask. More... | |
| #define | XDSI_CCR_RESET_DATA_FIFO_MASK 0x00000010 |
| Data FIFO Reset bit Mask. More... | |
| #define | XDSI_CCR_CRREADY_MASK 0x00000004 |
| Controller Ready bit Mask. More... | |
| #define | XDSI_CCR_SOFTRESET_MASK 0x00000002 |
| Soft Reset core bit Mask. More... | |
| #define | XDSI_CCR_COREENB_MASK 0x00000001 |
| Enable/Disable core Mask. More... | |
| #define | XDSI_CCR_CORECMDMODE_MASK 0x00000008 |
| Enable/Disable Command/video mode Mask. More... | |
| #define | XDSI_CCR_CORECMDMODE_SHIFT 3 |
| Shift for selection of command/video mode. More... | |
| #define | XDSI_CCR_CRREADY_SHIFT 2 |
| Shift for Controller Ready. More... | |
| #define | XDSI_CCR_SOFTRESET_SHIFT 1 |
| Shift for Soft reset. More... | |
| #define | XDSI_CCR_COREENB_SHIFT 0 |
| Shift for Core Enable. More... | |
Bitmasks and shifts of Protocol control register | |
This register reports the number of lanes configured during core generation and number of lanes actively used. | |
| #define | XDSI_PCR_EOTPENABLE_MASK 0x00002000 |
| End of Transmission Mask bit. More... | |
| #define | XDSI_PCR_PIXELFORMAT_MASK 0x00001F80 |
| Pixel Format Type Bit Mask. More... | |
| #define | XDSI_PCR_BLLPMODE_MASK 0x00000040 |
| Blank packet Mode Bit Mask. More... | |
| #define | XDSI_PCR_BLLPTYPE_MASK 0x00000020 |
| Blank packet type Bit Mask. More... | |
| #define | XDSI_PCR_VIDEOMODE_MASK 0x00000018 |
| Video mode Type Bit Mask. More... | |
| #define | XDSI_PCR_ACTLANES_MASK 0x00000003 |
| Active lanes in core. More... | |
| #define | XDSI_PCR_EOTPENABLE_SHIFT 13 |
| Shift for EOTP Enable. More... | |
| #define | XDSI_PCR_PIXELFORMAT_SHIFT 7 |
| Shift for pixel format. More... | |
| #define | XDSI_PCR_BLLPMODE_SHIFT 6 |
| Shift for Blank packet Type. More... | |
| #define | XDSI_PCR_BLLPTYPE_SHIFT 5 |
| Shift for Blank packet Type. More... | |
| #define | XDSI_PCR_VIDEOMODE_SHIFT 3 |
| Shift for Max Lanes. More... | |
| #define | XDSI_PCR_ACTLANES_SHIFT 0 |
| Shift for Active Lanes. More... | |
Bitmasks and shift of XDSI_STSTUS_OFFSET | |
This register used to get Command Queue Vacancy | |
| #define | XDSI_UNDER_PROCESS_MASK 0x00001000 |
| Command Underprocess. More... | |
| #define | XDSI_INPOGRESS_MASK 0x00000800 |
| Command InProgress. More... | |
| #define | XDSI_WAIT_FOR_DATA_MASK 0x00000400 |
| Wait for Long packet data. More... | |
| #define | XDSI_FIFO_EMPTY_MASK 0x00000200 |
| FIFO EMPTY. More... | |
| #define | XDSI_FIFO_FULL_MASK 0x00000100 |
| FIFO FULL. More... | |
| #define | XDSI_RDY_FOR_LONG_MASK 0x00000080 |
| Readiness for Long packet. More... | |
| #define | XDSI_RDY_FOR_SHORT_MASK 0x00000040 |
| Readiness for short packet. More... | |
| #define | XDSI_CMDQ_MASK 0x0000003F |
| Command Queue Vacancy. More... | |
| #define | XDSI_UNDER_PROCESS_SHIFT 12 |
| Command Underprocess. More... | |
| #define | XDSI_INPOGRESS_SHIFT 11 |
| Command InProgress. More... | |
| #define | XDSI_WAIT_FOR_DATA_SHIFT 10 |
| Wait for Long packet data. More... | |
| #define | XDSI_FIFO_EMPTY_SHIFT 9 |
| FIFO EMPTY. More... | |
| #define | XDSI_FIFO_FULL_SHIFT 8 |
| FIFO FULL. More... | |
| #define | XDSI_RDY_FOR_LONGPKT_SHIFT 7 |
| Readiness for Long packet. More... | |
| #define | XDSI_RDY_FOR_SHORTPKT_SHIFT 6 |
| Command Queue Vacancy. More... | |
| #define | XDSI_CMDQ_SHIFT 0 |
| Shift for Command Queue. More... | |
Bitmasks and shift of XDSI_TIME1_OFFSET | |
This register used to set timing parameters HSA and BLLP | |
| #define | XDSI_TIME1_HSA_MASK 0xFFFF0000 |
| Horizontal timing parameter HSA mask. More... | |
| #define | XDSI_TIME1_BLLP_BURST_MASK 0x0000FFFF |
| BLLP Packet size Mask bit. More... | |
| #define | XDSI_TIME1_HSA_SHIFT 16 |
| Shift for HSA. More... | |
| #define | XDSI_TIME1_BLLP_BURST_SHIFT 0 |
| Shift for BLLP. More... | |
Bitmasks and shift of XDSI_TIME2_OFFSET | |
This register used to set timing parameters | |
| #define | XDSI_TIME2_HACT_MASK 0xFFFF0000 |
| Horizontal timing parameter HACT Bit Mask. More... | |
| #define | XDSI_TIME2_VACT_MASK 0x0000FFFF |
| Vertical timing parameter VACT. More... | |
| #define | XDSI_TIME2_HACT_SHIFT 16 |
| Shift for HACT. More... | |
| #define | XDSI_TIME2_VACT_SHIFT 0 |
| Shift for VACT. More... | |
Bitmasks and shift of XDSI_TIME3_OFFSET | |
This register used to set timing parameters | |
| #define | XDSI_TIME3_HBP_MASK 0xFFFF0000 |
| Horizontal timing parameter HBP Bit Mask. More... | |
| #define | XDSI_TIME3_HFP_MASK 0x0000FFFF |
| Horizontal timing parameter HFP. More... | |
| #define | XDSI_TIME3_HBP_SHIFT 16 |
| Shift for HBP. More... | |
| #define | XDSI_TIME3_HFP_SHIFT 0 |
| Shift for HFP. More... | |
Bitmasks and offset of XDSI_TIME4_OFFSET | |
This register used to set Vertical timing parameters | |
| #define | XDSI_TIME4_VSA_MASK 0x00FF0000 |
| Time 4 Vertical Sync Active Mask. More... | |
| #define | XDSI_TIME4_VBP_MASK 0x0000FF00 |
| Vertical timing parameter1 VBP. More... | |
| #define | XDSI_TIME4_VFP_MASK 0x000000FF |
| Vertical timing parameter1 VFP. More... | |
| #define | XDSI_TIME4_VSA_SHIFT 16 |
| Shift for VSA. More... | |
| #define | XDSI_TIME4_VBP_SHIFT 8 |
| Shift for VBP. More... | |
| #define | XDSI_TIME4_VFP_SHIFT 0 |
| Shift for VFP. More... | |
Bitmasks and offset of XDSI_TIME5_OFFSET | |
This register used to set Extended vertical timing parameters It stores MSB 8-bits of 16-bit Vertical front porch lines count. | |
| #define | XDSI_TIME5_VFP_MASK 0x000000FF |
| Vertical extended timing parameter1 VFP. More... | |
| #define | XDSI_TIME5_VFP_SHIFT 0 |
| Shift for VFP. More... | |
Bitmasks and offsets of XDSI_GIER_OFFSET register | |
This register contains the global interrupt enable bit. | |
| #define | XDSI_GIER_GIE_MASK 0x00000001 |
| Global Interrupt Enable bit. More... | |
| #define | XDSI_GIER_GIE_SHIFT 0 |
| Shift bits for Global Interrupt Enable. More... | |
| #define | XDSI_GIER_SET 1 |
| Enable the Global Interrupts. More... | |
| #define | XDSI_GIER_RESET 0 |
| Disable the Global Interrupts. More... | |
Bitmasks and offsets of XDSI_ISR_OFFSET register | |
This register contains the interrupt status. | |
| #define | XDSI_ISR_CMDQ_FIFO_FULL_MASK 0x00000004 |
| Command queue vacancy full. More... | |
| #define | XDSI_ISR_DATA_ID_ERR_MASK 0x00000002 |
| Unsupport datatype Error. More... | |
| #define | XDSI_ISR_PXL_UNDR_RUN_MASK 0x00000001 |
| Pixel under run error. More... | |
| #define | XDSI_ISR_ALLINTR_MASK 0x00000007 |
| All interrupts mask. More... | |
| #define | XDSI_ISR_DATA_ID_ERR_SHIFT 1 |
| Shift for Unsupport Data Type. More... | |
| #define | XDSI_ISR_PXL_UNDR_RUN_SHIFT 0 |
| Shift for Pixel under run. More... | |
Bitmasks and offsets of XDSI_IER_OFFSET register | |
This register contains the interrupt enable masks | |
| #define | XDSI_IER_CMDQ_FIFO_FULL_MASK 0x00000004 |
| Command queue vacancy full. More... | |
| #define | XDSI_IER_DATA_ID_ERR_MASK 0x00000002 |
| Un supported data type. More... | |
| #define | XDSI_IER_PXL_UNDR_RUN_MASK 0x00000001 |
| Pixel Under run. More... | |
| #define | XDSI_IER_ALLINTR_MASK 0x00000007 |
| All interrupts mask. More... | |
| #define | XDSI_IER_DATA_ID_ERR_SHIFT 1 |
| Shift for Unsupport data type. More... | |
| #define | XDSI_IER_PXL_UNDR_RUN_SHIFT 0 |
| Shift for Pixel under run. More... | |
Bitmasks and offsets of XDSI_COMMAND_OFFSET register | |
This register contains the short packet command TBD as now | |
| #define | XDSI_SPKTR_DT_MASK 0x0000003F |
| Data Type. More... | |
| #define | XDSI_SPKTR_VC_MASK 0x000000C0 |
| Virtual channel number. More... | |
| #define | XDSI_SPKTR_BYTE1_MASK 0x0000FF00 |
| BYTE1 mask. More... | |
| #define | XDSI_SPKTR_BYTE2_MASK 0x00FF0000 |
| BYTE2 maks. More... | |
| #define | XDSI_SPKTR_DT_SHIFT 0 |
| Shift for DataType. More... | |
| #define | XDSI_SPKTR_VC_SHIFT 6 |
| Shift for VC. More... | |
| #define | XDSI_SPKTR_BYTE1_SHIFT 8 |
| Shift for BYTE1. More... | |
| #define | XDSI_SPKTR_BYTE2_SHIFT 16 |
| Shift for BYTE2. More... | |
Bitmasks and offsets of XDSI_LTIME_OFFSET register | |
This register contains the Total Line Time | |
| #define | XDSI_LTIME_MASK 0xFFFFFFFF |
| Total Line time. More... | |
| #define | XDSI_LTIME_SHIFT 0 |
| Shift for DataType. More... | |
Bitmasks and offsets of XDSI_BBLP_SIZE_OFFSET register | |
This register contains the BLLP Time duration | |
| #define | XDSI_BLLP_TIME_MASK 0xFFFFFFFF |
| BLLP Size. More... | |
| #define | XDSI_BLLP_TIME_SHIFT 0 |
| Shift for BLLP. More... | |