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gpio
Vitis Drivers API Documentation
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gpio
Vitis Drivers API Documentation
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Macros | |
| #define | XGPIO_L_H |
| by using protection macros More... | |
| #define | XGPIO_CHAN_OFFSET 8 |
| Channel offeset. More... | |
| #define | XGpio_In32 Xil_In32 |
| Input Operations. More... | |
| #define | XGpio_Out32 Xil_Out32 |
| Output Operations. More... | |
| #define | XGpio_WriteReg(BaseAddress, RegOffset, Data) XGpio_Out32((BaseAddress) + (RegOffset), (u32)(Data)) |
| Performs a 32-bit write to a GPIO register. More... | |
| #define | XGpio_ReadReg(BaseAddress, RegOffset) XGpio_In32((BaseAddress) + (RegOffset)) |
| Reads a value from a GPIO register. More... | |
Registers | |
Register offsets for this device. | |
| #define | XGPIO_DATA_OFFSET 0x0 |
| Data register for 1st channel. More... | |
| #define | XGPIO_TRI_OFFSET 0x4 |
| I/O direction reg for 1st channel. More... | |
| #define | XGPIO_DATA2_OFFSET 0x8 |
| Data register for 2nd channel. More... | |
| #define | XGPIO_TRI2_OFFSET 0xC |
| I/O direction reg for 2nd channel. More... | |
| #define | XGPIO_GIE_OFFSET 0x11C |
| Glogal interrupt enable register. More... | |
| #define | XGPIO_ISR_OFFSET 0x120 |
| Interrupt status register. More... | |
| #define | XGPIO_IER_OFFSET 0x128 |
| Interrupt enable register. More... | |
Interrupt Status and Enable Register bitmaps and masks | |
Bit definitions for the interrupt status register and interrupt enable registers. | |
| #define | XGPIO_IR_MASK 0x3 |
| Mask of all bits. More... | |
| #define | XGPIO_IR_CH1_MASK 0x1 |
| Mask for the 1st channel. More... | |
| #define | XGPIO_IR_CH2_MASK 0x2 |
| Mask for the 2nd channel. More... | |
Global Interrupt Enable Register bitmaps and masks | |
Bit definitions for the Global Interrupt Enable register | |
| #define | XGPIO_GIE_GINTR_ENABLE_MASK 0x80000000 |
| Mask for Global Interrupt. More... | |