i3cpsx
Vitis Drivers API Documentation
Macros
xi3cpsx_hw.h File Reference

Macros

#define XI3CPSX_HW_H_
 < prevent circular inclusions More...
 
#define XI3CPSX_BASEADDR   0x8000
 PS_I2C_I3C0 Base Address #define XI3CPSX_BASEADDR 0xF1000000 #define XI3CPSX_BASEADDR 0xF1940000 #define XI3CPSX_BASEADDR 0xF1950000. More...
 
#define XI3cPsx_ReadReg(BaseAddress, RegOffset)   XI3cPsx_In32((BaseAddress) + (u32)(RegOffset))
 Read an I3C register. More...
 
#define XI3cPsx_WriteReg(BaseAddress, RegOffset, RegisterValue)   XI3cPsx_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
 Write an I3C register. More...
 
#define XI3cPsx_WrFifoLevel(InstancePtr)
 Read Tx FIFO level. More...
 
#define XI3cPsx_RdFifoLevel(InstancePtr)
 Read Rx FIFO level. More...
 
#define XI3cPsx_EnableInterrupts(BaseAddress, IntrMask)
 Enable interrupts. More...
 
#define XI3cPsx_DisableInterrupts(BaseAddress, IntrMask)
 Disable interrupts. More...
 
#define XI3CPSX_DEVICE_CTRL   XI3CPSX_BASEADDR
 Register: XI3CPSX_DEVICE_CTRL. More...
 
#define XI3CPSX_DEVICE_ADDR   ( ( XI3CPSX_BASEADDR ) + 0x00000004 )
 Register: XI3CPSX_DEVICE_ADDR. More...
 
#define XI3CPSX_HW_CAPABILITY   ( ( XI3CPSX_BASEADDR ) + 0x00000008 )
 Register: XI3CPSX_HW_CAPABILITY. More...
 
#define XI3CPSX_COMMAND_QUEUE_PORT   ( ( XI3CPSX_BASEADDR ) + 0x0000000C )
 Register: XI3CPSX_COMMAND_QUEUE_PORT. More...
 
#define XI3CPSX_RESPONSE_QUEUE_PORT   ( ( XI3CPSX_BASEADDR ) + 0x00000010 )
 Register: XI3CPSX_RESPONSE_QUEUE_PORT. More...
 
#define XI3CPSX_TX_RX_DATA_PORT   ( ( XI3CPSX_BASEADDR ) + 0x00000014 )
 Register: XI3CPSX_TX_RX_DATA_PORT. More...
 
#define XI3CPSX_IBI_QUEUE_STATUS   ( ( XI3CPSX_BASEADDR ) + 0x00000018 )
 Register: XI3CPSX_IBI_QUEUE_STATUS. More...
 
#define XI3CPSX_QUEUE_THLD_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x0000001C )
 Register: XI3CPSX_QUEUE_THLD_CTRL. More...
 
#define XI3CPSX_DATA_BUFFER_THLD_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x00000020 )
 Register: XI3CPSX_DATA_BUFFER_THLD_CTRL. More...
 
#define XI3CPSX_IBI_QUEUE_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x00000024 )
 Register: XI3CPSX_IBI_QUEUE_CTRL. More...
 
#define XI3CPSX_IBI_MR_REQ_REJECT   ( ( XI3CPSX_BASEADDR ) + 0x0000002C )
 Register: XI3CPSX_IBI_MR_REQ_REJECT. More...
 
#define XI3CPSX_IBI_SIR_REQ_REJECT   ( ( XI3CPSX_BASEADDR ) + 0x00000030 )
 Register: XI3CPSX_IBI_SIR_REQ_REJECT. More...
 
#define XI3CPSX_RESET_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x00000034 )
 Register: XI3CPSX_RESET_CTRL. More...
 
#define XI3CPSX_SLV_EVENT_STATUS   ( ( XI3CPSX_BASEADDR ) + 0x00000038 )
 Register: XI3CPSX_SLV_EVENT_STATUS. More...
 
#define XI3CPSX_INTR_STATUS   ( ( XI3CPSX_BASEADDR ) + 0x0000003C )
 Register: XI3CPSX_INTR_STATUS. More...
 
#define XI3CPSX_INTR_STATUS_EN   ( ( XI3CPSX_BASEADDR ) + 0x00000040 )
 Register: XI3CPSX_INTR_STATUS_EN. More...
 
#define XI3CPSX_INTR_SIGNAL_EN   ( ( XI3CPSX_BASEADDR ) + 0x00000044 )
 Register: XI3CPSX_INTR_SIGNAL_EN. More...
 
#define XI3CPSX_INTR_FORCE   ( ( XI3CPSX_BASEADDR ) + 0x00000048 )
 Register: XI3CPSX_INTR_FORCE. More...
 
interrupt Register (INTR) mask(s)
#define XI3CPSX_INTR_TX_THLD   0x00000001
 BIT 0 - Transmit Buffer Threshold. More...
 
#define XI3CPSX_INTR_RX_THLD   0x00000002
 BIT 1 - Receive Buffer Threshold. More...
 
#define XI3CPSX_INTR_IBI_THLD   0x00000004
 BIT 2 - IBI Buffer Threshold. More...
 
#define XI3CPSX_INTR_CMD_QUEUE_READY   0x00000008
 BIT 3 - Command Queue Ready. More...
 
#define XI3CPSX_INTR_RESP_READY   0x00000010
 BIT 4 - Response Queue Ready. More...
 
#define XI3CPSX_INTR_TRANSFER_ABORT   0x00000020
 BIT 5 - Transfer Abort. More...
 
#define XI3CPSX_INTR_CCC_UPDATED   0x00000040
 BIT 6 - CCC Table Updated. More...
 
#define XI3CPSX_INTR_DYN_ADDR_ASSGN   0x00000100
 BIT 8 - Dynamic Address Assigned - only in slave mode. More...
 
#define XI3CPSX_INTR_TRANSFER_ERR   0x00000200
 BIT 9 - Transfer Error. More...
 
#define XI3CPSX_INTR_DEFSLV   0x00000400
 BIT 10 - Define Slave CCC Received. More...
 
#define XI3CPSX_INTR_READ_REQ_RECV   0x00000800
 BIT 11 - Read Request Received. More...
 
#define XI3CPSX_INTR_IBI_UPDATED   0x00001000
 BIT 12 - IBI status is updated. More...
 
#define XI3CPSX_INTR_BUSOWNER_UPDATED   0x00002000
 BIT 13 - Role of the controller changes from being a Master to Slave or vice versa. More...
 
#define XI3CPSX_INTR_BUS_RESET_DONE   0x00008000
 BIT 15 - Bus Reset Pattern Generation Done. More...
 
#define XI3CPSX_QUEUE_STATUS_LEVEL   ( ( XI3CPSX_BASEADDR ) + 0x0000004C )
 Register: XI3CPSX_QUEUE_STATUS_LEVEL. More...
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_FULLMASK   0x1fffffff
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_FULLRWMASK   0x00000000
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_DEFVAL   0x8
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_STS_CNT_SHIFT   24
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_STS_CNT_WIDTH   5
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_STS_CNT_MASK   0x1f000000
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_STS_CNT_DEFVAL   0x0
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_BUF_BLR_SHIFT   16
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_BUF_BLR_WIDTH   8
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_BUF_BLR_MASK   0x00ff0000
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_IBI_BUF_BLR_DEFVAL   0x0
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_SHIFT   8
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_WIDTH   8
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_MASK   0x0000ff00
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_RESP_BUF_BLR_DEFVAL   0x0
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_CMD_QUEUE_EMPTY_LOC_SHIFT   0
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_CMD_QUEUE_EMPTY_LOC_WIDTH   8
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_CMD_QUEUE_EMPTY_LOC_MASK   0x000000ff
 
#define XI3CPSX_QUEUE_STATUS_LEVEL_CMD_QUEUE_EMPTY_LOC_DEFVAL   0x8
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL   ( ( XI3CPSX_BASEADDR ) + 0x00000050 )
 Register: XI3CPSX_DATA_BUFFER_STATUS_LEVEL. More...
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_FULLMASK   0x00ff00ff
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_FULLRWMASK   0x00000000
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_DEFVAL   0x20
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_RX_BUF_BLR_SHIFT   16
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_RX_BUF_BLR_WIDTH   8
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_RX_BUF_BLR_MASK   0x00ff0000
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_RX_BUF_BLR_DEFVAL   0x0
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC_SHIFT   0
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC_WIDTH   8
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC_MASK   0x000000ff
 
#define XI3CPSX_DATA_BUFFER_STATUS_LEVEL_TX_BUF_EMPTY_LOC_DEFVAL   0x20
 
#define XI3CPSX_PRESENT_STATE   ( ( XI3CPSX_BASEADDR ) + 0x00000054 )
 Register: XI3CPSX_PRESENT_STATE. More...
 
#define XI3CPSX_PRESENT_STATE_FULLMASK   0x1f3f3f07
 
#define XI3CPSX_PRESENT_STATE_FULLRWMASK   0x00000000
 
#define XI3CPSX_PRESENT_STATE_DEFVAL   0x10000007
 
#define XI3CPSX_PRESENT_STATE_MASTER_IDLE_SHIFT   28
 
#define XI3CPSX_PRESENT_STATE_MASTER_IDLE_WIDTH   1
 
#define XI3CPSX_PRESENT_STATE_MASTER_IDLE_MASK   0x10000000
 
#define XI3CPSX_PRESENT_STATE_MASTER_IDLE_DEFVAL   0x1
 
#define XI3CPSX_PRESENT_STATE_CMD_TID_SHIFT   24
 
#define XI3CPSX_PRESENT_STATE_CMD_TID_WIDTH   4
 
#define XI3CPSX_PRESENT_STATE_CMD_TID_MASK   0x0f000000
 
#define XI3CPSX_PRESENT_STATE_CMD_TID_DEFVAL   0x0
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_ST_STS_SHIFT   16
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_ST_STS_WIDTH   6
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_ST_STS_MASK   0x003f0000
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_ST_STS_DEFVAL   0x0
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_STS_SHIFT   8
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_STS_WIDTH   6
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_STS_MASK   0x00003f00
 
#define XI3CPSX_PRESENT_STATE_CM_TFR_STS_DEFVAL   0x0
 
#define XI3CPSX_PRESENT_STATE_CURRENT_MASTER_SHIFT   2
 
#define XI3CPSX_PRESENT_STATE_CURRENT_MASTER_WIDTH   1
 
#define XI3CPSX_PRESENT_STATE_CURRENT_MASTER_MASK   0x00000004
 
#define XI3CPSX_PRESENT_STATE_CURRENT_MASTER_DEFVAL   0x1
 
#define XI3CPSX_PRESENT_STATE_SDA_LINE_SIGNAL_LEVEL_SHIFT   1
 
#define XI3CPSX_PRESENT_STATE_SDA_LINE_SIGNAL_LEVEL_WIDTH   1
 
#define XI3CPSX_PRESENT_STATE_SDA_LINE_SIGNAL_LEVEL_MASK   0x00000002
 
#define XI3CPSX_PRESENT_STATE_SDA_LINE_SIGNAL_LEVEL_DEFVAL   0x1
 
#define XI3CPSX_PRESENT_STATE_SCL_LINE_SIGNAL_LEVEL_SHIFT   0
 
#define XI3CPSX_PRESENT_STATE_SCL_LINE_SIGNAL_LEVEL_WIDTH   1
 
#define XI3CPSX_PRESENT_STATE_SCL_LINE_SIGNAL_LEVEL_MASK   0x00000001
 
#define XI3CPSX_PRESENT_STATE_SCL_LINE_SIGNAL_LEVEL_DEFVAL   0x1
 
#define XI3CPSX_CCC_DEVICE_STATUS   ( ( XI3CPSX_BASEADDR ) + 0x00000058 )
 Register: XI3CPSX_CCC_DEVICE_STATUS. More...
 
#define XI3CPSX_CCC_DEVICE_STATUS_FULLMASK   0x00003fef
 
#define XI3CPSX_CCC_DEVICE_STATUS_FULLRWMASK   0x00000000
 
#define XI3CPSX_CCC_DEVICE_STATUS_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_FRAME_ERROR_SHIFT   13
 
#define XI3CPSX_CCC_DEVICE_STATUS_FRAME_ERROR_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_FRAME_ERROR_MASK   0x00002000
 
#define XI3CPSX_CCC_DEVICE_STATUS_FRAME_ERROR_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_BUFFER_NOT_AVAIL_SHIFT   12
 
#define XI3CPSX_CCC_DEVICE_STATUS_BUFFER_NOT_AVAIL_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_BUFFER_NOT_AVAIL_MASK   0x00001000
 
#define XI3CPSX_CCC_DEVICE_STATUS_BUFFER_NOT_AVAIL_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_DATA_NOT_READY_SHIFT   11
 
#define XI3CPSX_CCC_DEVICE_STATUS_DATA_NOT_READY_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_DATA_NOT_READY_MASK   0x00000800
 
#define XI3CPSX_CCC_DEVICE_STATUS_DATA_NOT_READY_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_OVERFLOW_ERR_SHIFT   10
 
#define XI3CPSX_CCC_DEVICE_STATUS_OVERFLOW_ERR_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_OVERFLOW_ERR_MASK   0x00000400
 
#define XI3CPSX_CCC_DEVICE_STATUS_OVERFLOW_ERR_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_SLAVE_BUSY_SHIFT   9
 
#define XI3CPSX_CCC_DEVICE_STATUS_SLAVE_BUSY_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_SLAVE_BUSY_MASK   0x00000200
 
#define XI3CPSX_CCC_DEVICE_STATUS_SLAVE_BUSY_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_UNDERFLOW_ERR_SHIFT   8
 
#define XI3CPSX_CCC_DEVICE_STATUS_UNDERFLOW_ERR_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_UNDERFLOW_ERR_MASK   0x00000100
 
#define XI3CPSX_CCC_DEVICE_STATUS_UNDERFLOW_ERR_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_ACTIVITY_MODE_SHIFT   6
 
#define XI3CPSX_CCC_DEVICE_STATUS_ACTIVITY_MODE_WIDTH   2
 
#define XI3CPSX_CCC_DEVICE_STATUS_ACTIVITY_MODE_MASK   0x000000c0
 
#define XI3CPSX_CCC_DEVICE_STATUS_ACTIVITY_MODE_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_PROTOCOL_ERR_SHIFT   5
 
#define XI3CPSX_CCC_DEVICE_STATUS_PROTOCOL_ERR_WIDTH   1
 
#define XI3CPSX_CCC_DEVICE_STATUS_PROTOCOL_ERR_MASK   0x00000020
 
#define XI3CPSX_CCC_DEVICE_STATUS_PROTOCOL_ERR_DEFVAL   0x0
 
#define XI3CPSX_CCC_DEVICE_STATUS_PENDING_INTR_SHIFT   0
 
#define XI3CPSX_CCC_DEVICE_STATUS_PENDING_INTR_WIDTH   4
 
#define XI3CPSX_CCC_DEVICE_STATUS_PENDING_INTR_MASK   0x0000000f
 
#define XI3CPSX_CCC_DEVICE_STATUS_PENDING_INTR_DEFVAL   0x0
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER   ( ( XI3CPSX_BASEADDR ) + 0x0000005C )
 Register: XI3CPSX_DEVICE_ADDR_TABLE_POINTER. More...
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_FULLMASK   0xffffffff
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_DEFVAL   0xb02c0
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_DEV_ADDR_TABLE_DEPTH_SHIFT   16
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_DEV_ADDR_TABLE_DEPTH_WIDTH   16
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_DEV_ADDR_TABLE_DEPTH_MASK   0xffff0000
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_DEV_ADDR_TABLE_DEPTH_DEFVAL   0xb
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_P_DEV_ADDR_TABLE_START_ADDR_SHIFT   0
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_P_DEV_ADDR_TABLE_START_ADDR_WIDTH   16
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_P_DEV_ADDR_TABLE_START_ADDR_MASK   0x0000ffff
 
#define XI3CPSX_DEVICE_ADDR_TABLE_POINTER_P_DEV_ADDR_TABLE_START_ADDR_DEFVAL   0x2c0
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER   ( ( XI3CPSX_BASEADDR ) + 0x00000060 )
 Register: XI3CPSX_DEV_CHAR_TABLE_POINTER. More...
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_FULLMASK   0x007fffff
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_FULLRWMASK   0x00780000
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_DEFVAL   0x2c200
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_PRESENT_DEV_CHAR_TABLE_INDX_SHIFT   19
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_PRESENT_DEV_CHAR_TABLE_INDX_WIDTH   4
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_PRESENT_DEV_CHAR_TABLE_INDX_MASK   0x00780000
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_PRESENT_DEV_CHAR_TABLE_INDX_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_DEV_CHAR_TABLE_DEPTH_SHIFT   12
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_DEV_CHAR_TABLE_DEPTH_WIDTH   7
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_DEV_CHAR_TABLE_DEPTH_MASK   0x0007f000
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_DEV_CHAR_TABLE_DEPTH_DEFVAL   0x2c
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_P_DEV_CHAR_TABLE_START_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_P_DEV_CHAR_TABLE_START_ADDR_WIDTH   12
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_P_DEV_CHAR_TABLE_START_ADDR_MASK   0x00000fff
 
#define XI3CPSX_DEV_CHAR_TABLE_POINTER_P_DEV_CHAR_TABLE_START_ADDR_DEFVAL   0x200
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER   ( ( XI3CPSX_BASEADDR ) + 0x0000006C )
 Register: XI3CPSX_VENDOR_SPECIFIC_REG_POINTER. More...
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_FULLMASK   0x0000ffff
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_FULLRWMASK   0x00000000
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_DEFVAL   0xb0
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_P_VENDOR_REG_START_ADDR_SHIFT   0
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_P_VENDOR_REG_START_ADDR_WIDTH   16
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_P_VENDOR_REG_START_ADDR_MASK   0x0000ffff
 
#define XI3CPSX_VENDOR_SPECIFIC_REG_POINTER_P_VENDOR_REG_START_ADDR_DEFVAL   0xb0
 
#define XI3CPSX_SLV_MIPI_ID_VALUE   ( ( XI3CPSX_BASEADDR ) + 0x00000070 )
 Register: XI3CPSX_SLV_MIPI_ID_VALUE. More...
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_FULLMASK   0x0000ffff
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_FULLRWMASK   0x0000ffff
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_DEFVAL   0x0
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_SHIFT   1
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_WIDTH   15
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_MASK   0x0000fffe
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_MIPI_MFG_ID_DEFVAL   0x0
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL_SHIFT   0
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL_WIDTH   1
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL_MASK   0x00000001
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL_DEFVAL   0x0
 
#define XI3CPSX_SLV_MIPI_ID_VALUE_SLV_PROV_ID_SEL_VAL   0x2
 
#define XI3CPSX_SLV_PID_VALUE   ( ( XI3CPSX_BASEADDR ) + 0x00000074 )
 Register: XI3CPSX_SLV_PID_VALUE. More...
 
#define XI3CPSX_SLV_PID_VALUE_FULLMASK   0xffffffff
 
#define XI3CPSX_SLV_PID_VALUE_FULLRWMASK   0xffffffff
 
#define XI3CPSX_SLV_PID_VALUE_DEFVAL   0x0
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PART_ID_SHIFT   16
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PART_ID_WIDTH   16
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PART_ID_MASK   0xffff0000
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PART_ID_DEFVAL   0x0
 
#define XI3CPSX_SLV_PID_VALUE_SLV_INST_ID_SHIFT   12
 
#define XI3CPSX_SLV_PID_VALUE_SLV_INST_ID_WIDTH   4
 
#define XI3CPSX_SLV_PID_VALUE_SLV_INST_ID_MASK   0x0000f000
 
#define XI3CPSX_SLV_PID_VALUE_SLV_INST_ID_DEFVAL   0x0
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PID_DCR_SHIFT   0
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PID_DCR_WIDTH   12
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PID_DCR_MASK   0x00000fff
 
#define XI3CPSX_SLV_PID_VALUE_SLV_PID_DCR_DEFVAL   0x0
 
#define XI3CPSX_SLV_CHAR_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x00000078 )
 Register: XI3CPSX_SLV_CHAR_CTRL. More...
 
#define XI3CPSX_SLV_CHAR_CTRL_FULLMASK   0x00ffffff
 
#define XI3CPSX_SLV_CHAR_CTRL_FULLRWMASK   0x0000ffe1
 
#define XI3CPSX_SLV_CHAR_CTRL_DEFVAL   0x10062
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAP_SHIFT   16
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAP_WIDTH   8
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAP_MASK   0x00ff0000
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAP_DEFVAL   0x1
 
#define XI3CPSX_SLV_CHAR_CTRL_DCR_SHIFT   8
 
#define XI3CPSX_SLV_CHAR_CTRL_DCR_WIDTH   8
 
#define XI3CPSX_SLV_CHAR_CTRL_DCR_MASK   0x0000ff00
 
#define XI3CPSX_SLV_CHAR_CTRL_DCR_DEFVAL   0x0
 
#define XI3CPSX_SLV_CHAR_CTRL_DCR_VAL   0xC4
 
#define XI3CPSX_SLV_CHAR_CTRL_DEVICE_ROLE_SHIFT   6
 
#define XI3CPSX_SLV_CHAR_CTRL_DEVICE_ROLE_WIDTH   2
 
#define XI3CPSX_SLV_CHAR_CTRL_DEVICE_ROLE_MASK   0x000000c0
 
#define XI3CPSX_SLV_CHAR_CTRL_DEVICE_ROLE_DEFVAL   0x1
 
#define XI3CPSX_SLV_CHAR_CTRL_DEVICE_ROLE_SLAVE   0x2
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAPABLE_SHIFT   5
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAPABLE_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAPABLE_MASK   0x00000020
 
#define XI3CPSX_SLV_CHAR_CTRL_HDR_CAPABLE_DEFVAL   0x1
 
#define XI3CPSX_SLV_CHAR_CTRL_BRIDGE_IDENTIFIER_SHIFT   4
 
#define XI3CPSX_SLV_CHAR_CTRL_BRIDGE_IDENTIFIER_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_BRIDGE_IDENTIFIER_MASK   0x00000010
 
#define XI3CPSX_SLV_CHAR_CTRL_BRIDGE_IDENTIFIER_DEFVAL   0x0
 
#define XI3CPSX_SLV_CHAR_CTRL_OFFLINE_CAPABLE_SHIFT   3
 
#define XI3CPSX_SLV_CHAR_CTRL_OFFLINE_CAPABLE_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_OFFLINE_CAPABLE_MASK   0x00000008
 
#define XI3CPSX_SLV_CHAR_CTRL_OFFLINE_CAPABLE_DEFVAL   0x0
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_PAYLOAD_SHIFT   2
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_PAYLOAD_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_PAYLOAD_MASK   0x00000004
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_PAYLOAD_DEFVAL   0x0
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_REQUEST_CAPABLE_SHIFT   1
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_REQUEST_CAPABLE_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_REQUEST_CAPABLE_MASK   0x00000002
 
#define XI3CPSX_SLV_CHAR_CTRL_IBI_REQUEST_CAPABLE_DEFVAL   0x1
 
#define XI3CPSX_SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT_SHIFT   0
 
#define XI3CPSX_SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT_WIDTH   1
 
#define XI3CPSX_SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT_MASK   0x00000001
 
#define XI3CPSX_SLV_CHAR_CTRL_MAX_DATA_SPEED_LIMIT_DEFVAL   0x0
 
#define XI3CPSX_SLV_MAX_LEN   ( ( XI3CPSX_BASEADDR ) + 0x0000007C )
 Register: XI3CPSX_SLV_MAX_LEN. More...
 
#define XI3CPSX_SLV_MAX_LEN_FULLMASK   0xffffffff
 
#define XI3CPSX_SLV_MAX_LEN_FULLRWMASK   0x00000000
 
#define XI3CPSX_SLV_MAX_LEN_DEFVAL   0xff00ff
 
#define XI3CPSX_SLV_MAX_LEN_MRL_SHIFT   16
 
#define XI3CPSX_SLV_MAX_LEN_MRL_WIDTH   16
 
#define XI3CPSX_SLV_MAX_LEN_MRL_MASK   0xffff0000
 
#define XI3CPSX_SLV_MAX_LEN_MRL_DEFVAL   0xff
 
#define XI3CPSX_SLV_MAX_LEN_MWL_SHIFT   0
 
#define XI3CPSX_SLV_MAX_LEN_MWL_WIDTH   16
 
#define XI3CPSX_SLV_MAX_LEN_MWL_MASK   0x0000ffff
 
#define XI3CPSX_SLV_MAX_LEN_MWL_DEFVAL   0xff
 
#define XI3CPSX_MAX_READ_TURNAROUND   ( ( XI3CPSX_BASEADDR ) + 0x00000080 )
 Register: XI3CPSX_MAX_READ_TURNAROUND. More...
 
#define XI3CPSX_MAX_READ_TURNAROUND_FULLMASK   0x00ffffff
 
#define XI3CPSX_MAX_READ_TURNAROUND_FULLRWMASK   0x00000000
 
#define XI3CPSX_MAX_READ_TURNAROUND_DEFVAL   0x0
 
#define XI3CPSX_MAX_READ_TURNAROUND_MXDS_MAX_RD_TURN_SHIFT   0
 
#define XI3CPSX_MAX_READ_TURNAROUND_MXDS_MAX_RD_TURN_WIDTH   24
 
#define XI3CPSX_MAX_READ_TURNAROUND_MXDS_MAX_RD_TURN_MASK   0x00ffffff
 
#define XI3CPSX_MAX_READ_TURNAROUND_MXDS_MAX_RD_TURN_DEFVAL   0x0
 
#define XI3CPSX_MAX_DATA_SPEED   ( ( XI3CPSX_BASEADDR ) + 0x00000084 )
 Register: XI3CPSX_MAX_DATA_SPEED. More...
 
#define XI3CPSX_MAX_DATA_SPEED_FULLMASK   0x00070707
 
#define XI3CPSX_MAX_DATA_SPEED_FULLRWMASK   0x00070707
 
#define XI3CPSX_MAX_DATA_SPEED_DEFVAL   0x0
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_CLK_DATA_TURN_SHIFT   16
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_CLK_DATA_TURN_WIDTH   3
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_CLK_DATA_TURN_MASK   0x00070000
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_CLK_DATA_TURN_DEFVAL   0x0
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_RD_SPEED_SHIFT   8
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_RD_SPEED_WIDTH   3
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_RD_SPEED_MASK   0x00000700
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_RD_SPEED_DEFVAL   0x0
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_WR_SPEED_SHIFT   0
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_WR_SPEED_WIDTH   3
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_WR_SPEED_MASK   0x00000007
 
#define XI3CPSX_MAX_DATA_SPEED_MXDS_MAX_WR_SPEED_DEFVAL   0x0
 
#define XI3CPSX_SLV_INTR_REQ   ( ( XI3CPSX_BASEADDR ) + 0x0000008C )
 Register: XI3CPSX_SLV_INTR_REQ. More...
 
#define XI3CPSX_SLV_INTR_REQ_FULLMASK   0x0000030f
 
#define XI3CPSX_SLV_INTR_REQ_FULLRWMASK   0x0000000f
 
#define XI3CPSX_SLV_INTR_REQ_DEFVAL   0x0
 
#define XI3CPSX_SLV_INTR_REQ_IBI_STS_SHIFT   8
 
#define XI3CPSX_SLV_INTR_REQ_IBI_STS_WIDTH   2
 
#define XI3CPSX_SLV_INTR_REQ_IBI_STS_MASK   0x00000300
 
#define XI3CPSX_SLV_INTR_REQ_IBI_STS_DEFVAL   0x0
 
#define XI3CPSX_SLV_INTR_REQ_MR_SHIFT   3
 
#define XI3CPSX_SLV_INTR_REQ_MR_WIDTH   1
 
#define XI3CPSX_SLV_INTR_REQ_MR_MASK   0x00000008
 
#define XI3CPSX_SLV_INTR_REQ_MR_DEFVAL   0x0
 
#define XI3CPSX_SLV_INTR_REQ_SIR_CTRL_SHIFT   1
 
#define XI3CPSX_SLV_INTR_REQ_SIR_CTRL_WIDTH   2
 
#define XI3CPSX_SLV_INTR_REQ_SIR_CTRL_MASK   0x00000006
 
#define XI3CPSX_SLV_INTR_REQ_SIR_CTRL_DEFVAL   0x0
 
#define XI3CPSX_SLV_INTR_REQ_SIR_SHIFT   0
 
#define XI3CPSX_SLV_INTR_REQ_SIR_WIDTH   1
 
#define XI3CPSX_SLV_INTR_REQ_SIR_MASK   0x00000001
 
#define XI3CPSX_SLV_INTR_REQ_SIR_DEFVAL   0x0
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED   ( ( XI3CPSX_BASEADDR ) + 0x000000B0 )
 Register: XI3CPSX_DEVICE_CTRL_EXTENDED. More...
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_FULLMASK   0x0000000b
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_FULLRWMASK   0x0000000b
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEFVAL   0x0
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_REQMST_ACK_CTRL_SHIFT   3
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_REQMST_ACK_CTRL_WIDTH   1
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_REQMST_ACK_CTRL_MASK   0x00000008
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_REQMST_ACK_CTRL_DEFVAL   0x0
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_SHIFT   0
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_MASTER   0x0
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_SLAVE   0x1
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_WIDTH   2
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_MASK   0x00000003
 
#define XI3CPSX_DEVICE_CTRL_EXTENDED_DEV_OPERATION_MODE_DEFVAL   0x0
 
#define XI3CPSX_SCL_I3C_OD_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000B4 )
 Register: XI3CPSX_SCL_I3C_OD_TIMING. More...
 
#define XI3CPSX_SCL_I3C_OD_TIMING_FULLMASK   0x00ff00ff
 
#define XI3CPSX_SCL_I3C_OD_TIMING_FULLRWMASK   0x00ff00ff
 
#define XI3CPSX_SCL_I3C_OD_TIMING_DEFVAL   0xa0010
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_HCNT_SHIFT   16
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_HCNT_WIDTH   8
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_HCNT_MASK   0x00ff0000
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_HCNT_DEFVAL   0xa
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_HCNT_VAL   8
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_LCNT_SHIFT   0
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_LCNT_WIDTH   8
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_LCNT_MASK   0x000000ff
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_LCNT_DEFVAL   0x10
 
#define XI3CPSX_SCL_I3C_OD_TIMING_I3C_OD_LCNT_VAL   50
 
#define XI3CPSX_SCL_I3C_PP_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000B8 )
 Register: XI3CPSX_SCL_I3C_PP_TIMING. More...
 
#define XI3CPSX_SCL_I3C_PP_TIMING_FULLMASK   0x00ff00ff
 
#define XI3CPSX_SCL_I3C_PP_TIMING_FULLRWMASK   0x00ff00ff
 
#define XI3CPSX_SCL_I3C_PP_TIMING_DEFVAL   0xa000a
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_HCNT_SHIFT   16
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_HCNT_WIDTH   8
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_HCNT_MASK   0x00ff0000
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_HCNT_DEFVAL   0xa
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_HCNT_VAL   8
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_LCNT_SHIFT   0
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_LCNT_WIDTH   8
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_LCNT_MASK   0x000000ff
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_LCNT_DEFVAL   0xa
 
#define XI3CPSX_SCL_I3C_PP_TIMING_I3C_PP_LCNT_VAL   8
 
#define XI3CPSX_SCL_I2C_FM_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000BC )
 Register: XI3CPSX_SCL_I2C_FM_TIMING. More...
 
#define XI3CPSX_SCL_I2C_FM_TIMING_FULLMASK   0xffffffff
 
#define XI3CPSX_SCL_I2C_FM_TIMING_FULLRWMASK   0xffffffff
 
#define XI3CPSX_SCL_I2C_FM_TIMING_DEFVAL   0x100010
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_HCNT_SHIFT   16
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_HCNT_WIDTH   16
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_HCNT_MASK   0xffff0000
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_HCNT_DEFVAL   0x10
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_LCNT_SHIFT   0
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_LCNT_WIDTH   16
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_LCNT_MASK   0x0000ffff
 
#define XI3CPSX_SCL_I2C_FM_TIMING_I2C_FM_LCNT_DEFVAL   0x10
 
#define XI3CPSX_SCL_I2C_FMP_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000C0 )
 Register: XI3CPSX_SCL_I2C_FMP_TIMING. More...
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_FULLMASK   0x00ffffff
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_FULLRWMASK   0x00ffffff
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_DEFVAL   0x100010
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_I2C_FMP_HCNT_SHIFT   16
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_I2C_FMP_HCNT_WIDTH   8
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_I2C_FMP_HCNT_MASK   0x00ff0000
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_I2C_FMP_HCNT_DEFVAL   0x10
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_2C_FMP_LCNT_SHIFT   0
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_2C_FMP_LCNT_WIDTH   16
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_2C_FMP_LCNT_MASK   0x0000ffff
 
#define XI3CPSX_SCL_I2C_FMP_TIMING_2C_FMP_LCNT_DEFVAL   0x10
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000C8 )
 Register: XI3CPSX_SCL_EXT_LCNT_TIMING. More...
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_FULLMASK   0xffffffff
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_FULLRWMASK   0xffffffff
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_DEFVAL   0x20202020
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_4_SHIFT   24
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_4_WIDTH   8
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_4_MASK   0xff000000
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_4_DEFVAL   0x20
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_3_SHIFT   16
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_3_WIDTH   8
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_3_MASK   0x00ff0000
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_3_DEFVAL   0x20
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_2_SHIFT   8
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_2_WIDTH   8
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_2_MASK   0x0000ff00
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_2_DEFVAL   0x20
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_1_SHIFT   0
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_1_WIDTH   8
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_1_MASK   0x000000ff
 
#define XI3CPSX_SCL_EXT_LCNT_TIMING_I3C_EXT_LCNT_1_DEFVAL   0x20
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000CC )
 Register: XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING. More...
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_FULLMASK   0x0000000f
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_FULLRWMASK   0x0000000f
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_DEFVAL   0x0
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_I3C_EXT_TERMN_LCNT_SHIFT   0
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_I3C_EXT_TERMN_LCNT_WIDTH   4
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_I3C_EXT_TERMN_LCNT_MASK   0x0000000f
 
#define XI3CPSX_SCL_EXT_TERMN_LCNT_TIMING_I3C_EXT_TERMN_LCNT_DEFVAL   0x0
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000D0 )
 Register: XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING. More...
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_FULLMASK   0x00070000
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_FULLRWMASK   0x00070000
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_DEFVAL   0x10000
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_SDA_TX_HOLD_SHIFT   16
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_SDA_TX_HOLD_WIDTH   3
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_SDA_TX_HOLD_MASK   0x00070000
 
#define XI3CPSX_SDA_HOLD_SWITCH_DLY_TIMING_SDA_TX_HOLD_DEFVAL   0x1
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000D4 )
 Register: XI3CPSX_BUS_FREE_AVAIL_TIMING. More...
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_FULLMASK   0xffffffff
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_FULLRWMASK   0xffffffff
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_DEFVAL   0x200020
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_AVAILABLE_TIME_SHIFT   16
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_AVAILABLE_TIME_WIDTH   16
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_AVAILABLE_TIME_MASK   0xffff0000
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_AVAILABLE_TIME_DEFVAL   0x20
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_AVAILABLE_TIME_VAL   0xa0
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME_SHIFT   0
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME_WIDTH   16
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME_MASK   0x0000ffff
 
#define XI3CPSX_BUS_FREE_AVAIL_TIMING_BUS_FREE_TIME_DEFVAL   0x20
 
#define XI3CPSX_BUS_IDLE_TIMING   ( ( XI3CPSX_BASEADDR ) + 0x000000D8 )
 Register: XI3CPSX_BUS_IDLE_TIMING. More...
 
#define XI3CPSX_BUS_IDLE_TIMING_FULLMASK   0x000fffff
 
#define XI3CPSX_BUS_IDLE_TIMING_FULLRWMASK   0x000fffff
 
#define XI3CPSX_BUS_IDLE_TIMING_DEFVAL   0x20
 
#define XI3CPSX_BUS_IDLE_TIMING_BUS_IDLE_TIME_SHIFT   0
 
#define XI3CPSX_BUS_IDLE_TIMING_BUS_IDLE_TIME_WIDTH   20
 
#define XI3CPSX_BUS_IDLE_TIMING_BUS_IDLE_TIME_MASK   0x000fffff
 
#define XI3CPSX_BUS_IDLE_TIMING_BUS_IDLE_TIME_DEFVAL   0x20
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT   ( ( XI3CPSX_BASEADDR ) + 0x000000DC )
 Register: XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT. More...
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_FULLMASK   0x03ffffff
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_FULLRWMASK   0x03ffffff
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_DEFVAL   0x3567e0
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_SCL_LOW_MST_TIMEOUT_COUNT_SHIFT   0
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_SCL_LOW_MST_TIMEOUT_COUNT_WIDTH   26
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_SCL_LOW_MST_TIMEOUT_COUNT_MASK   0x03ffffff
 
#define XI3CPSX_SCL_LOW_MST_EXT_TIMEOUT_SCL_LOW_MST_TIMEOUT_COUNT_DEFVAL   0x3567e0
 
#define XI3CPSX_I3C_VER_ID   ( ( XI3CPSX_BASEADDR ) + 0x000000E0 )
 Register: XI3CPSX_I3C_VER_ID. More...
 
#define XI3CPSX_I3C_VER_ID_FULLMASK   0xffffffff
 
#define XI3CPSX_I3C_VER_ID_FULLRWMASK   0x00000000
 
#define XI3CPSX_I3C_VER_ID_DEFVAL   0x3130302a
 
#define XI3CPSX_I3C_VER_ID_I3C_VER_ID_SHIFT   0
 
#define XI3CPSX_I3C_VER_ID_I3C_VER_ID_WIDTH   32
 
#define XI3CPSX_I3C_VER_ID_I3C_VER_ID_MASK   0xffffffff
 
#define XI3CPSX_I3C_VER_ID_I3C_VER_ID_DEFVAL   0x3130302a
 
#define XI3CPSX_I3C_VER_TYPE   ( ( XI3CPSX_BASEADDR ) + 0x000000E4 )
 Register: XI3CPSX_I3C_VER_TYPE. More...
 
#define XI3CPSX_I3C_VER_TYPE_FULLMASK   0xffffffff
 
#define XI3CPSX_I3C_VER_TYPE_FULLRWMASK   0x00000000
 
#define XI3CPSX_I3C_VER_TYPE_DEFVAL   0x6c633033
 
#define XI3CPSX_I3C_VER_TYPE_I3C_VER_TYPE_SHIFT   0
 
#define XI3CPSX_I3C_VER_TYPE_I3C_VER_TYPE_WIDTH   32
 
#define XI3CPSX_I3C_VER_TYPE_I3C_VER_TYPE_MASK   0xffffffff
 
#define XI3CPSX_I3C_VER_TYPE_I3C_VER_TYPE_DEFVAL   0x6c633033
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY   ( ( XI3CPSX_BASEADDR ) + 0x000000E8 )
 Register: XI3CPSX_QUEUE_SIZE_CAPABILITY. More...
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_FULLMASK   0x000fffff
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_FULLRWMASK   0x00000000
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_DEFVAL   0x21244
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_IBI_BUF_SIZE_SHIFT   16
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_IBI_BUF_SIZE_WIDTH   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_IBI_BUF_SIZE_MASK   0x000f0000
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_IBI_BUF_SIZE_DEFVAL   0x2
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RESP_BUF_SIZE_SHIFT   12
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RESP_BUF_SIZE_WIDTH   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RESP_BUF_SIZE_MASK   0x0000f000
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RESP_BUF_SIZE_DEFVAL   0x1
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_CMD_BUF_SIZE_SHIFT   8
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_CMD_BUF_SIZE_WIDTH   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_CMD_BUF_SIZE_MASK   0x00000f00
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_CMD_BUF_SIZE_DEFVAL   0x2
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RX_BUF_SIZE_SHIFT   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RX_BUF_SIZE_WIDTH   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RX_BUF_SIZE_MASK   0x000000f0
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_RX_BUF_SIZE_DEFVAL   0x4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_TX_BUF_SIZE_SHIFT   0
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_TX_BUF_SIZE_WIDTH   4
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_TX_BUF_SIZE_MASK   0x0000000f
 
#define XI3CPSX_QUEUE_SIZE_CAPABILITY_TX_BUF_SIZE_DEFVAL   0x4
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000200 )
 Register: XI3CPSX_DEV_CHAR_TABLE1_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000204 )
 Register: XI3CPSX_DEV_CHAR_TABLE1_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000208 )
 Register: XI3CPSX_DEV_CHAR_TABLE1_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000020C )
 Register: XI3CPSX_DEV_CHAR_TABLE1_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE1_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000210 )
 Register: XI3CPSX_DEV_CHAR_TABLE2_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000214 )
 Register: XI3CPSX_DEV_CHAR_TABLE2_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000218 )
 Register: XI3CPSX_DEV_CHAR_TABLE2_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000021C )
 Register: XI3CPSX_DEV_CHAR_TABLE2_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE2_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000220 )
 Register: XI3CPSX_DEV_CHAR_TABLE3_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000224 )
 Register: XI3CPSX_DEV_CHAR_TABLE3_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000228 )
 Register: XI3CPSX_DEV_CHAR_TABLE3_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000022C )
 Register: XI3CPSX_DEV_CHAR_TABLE3_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE3_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000230 )
 Register: XI3CPSX_DEV_CHAR_TABLE4_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000234 )
 Register: XI3CPSX_DEV_CHAR_TABLE4_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000238 )
 Register: XI3CPSX_DEV_CHAR_TABLE4_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000023C )
 Register: XI3CPSX_DEV_CHAR_TABLE4_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE4_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000240 )
 Register: XI3CPSX_DEV_CHAR_TABLE5_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000244 )
 Register: XI3CPSX_DEV_CHAR_TABLE5_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000248 )
 Register: XI3CPSX_DEV_CHAR_TABLE5_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000024C )
 Register: XI3CPSX_DEV_CHAR_TABLE5_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE5_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000250 )
 Register: XI3CPSX_DEV_CHAR_TABLE6_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000254 )
 Register: XI3CPSX_DEV_CHAR_TABLE6_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000258 )
 Register: XI3CPSX_DEV_CHAR_TABLE6_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000025C )
 Register: XI3CPSX_DEV_CHAR_TABLE6_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE6_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000260 )
 Register: XI3CPSX_DEV_CHAR_TABLE7_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000264 )
 Register: XI3CPSX_DEV_CHAR_TABLE7_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000268 )
 Register: XI3CPSX_DEV_CHAR_TABLE7_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000026C )
 Register: XI3CPSX_DEV_CHAR_TABLE7_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE7_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000270 )
 Register: XI3CPSX_DEV_CHAR_TABLE8_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000274 )
 Register: XI3CPSX_DEV_CHAR_TABLE8_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000278 )
 Register: XI3CPSX_DEV_CHAR_TABLE8_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000027C )
 Register: XI3CPSX_DEV_CHAR_TABLE8_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE8_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000280 )
 Register: XI3CPSX_DEV_CHAR_TABLE9_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000284 )
 Register: XI3CPSX_DEV_CHAR_TABLE9_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000288 )
 Register: XI3CPSX_DEV_CHAR_TABLE9_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000028C )
 Register: XI3CPSX_DEV_CHAR_TABLE9_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE9_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x00000290 )
 Register: XI3CPSX_DEV_CHAR_TABLE10_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x00000294 )
 Register: XI3CPSX_DEV_CHAR_TABLE10_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x00000298 )
 Register: XI3CPSX_DEV_CHAR_TABLE10_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x0000029C )
 Register: XI3CPSX_DEV_CHAR_TABLE10_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE10_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x000002A0 )
 Register: XI3CPSX_DEV_CHAR_TABLE11_LOC1. More...
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_FULLMASK   0xffffffff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_STATIC_ADDR_SHIFT   24
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_STATIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_STATIC_ADDR_MASK   0xff000000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_BCR_TYPE_SHIFT   16
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_BCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_BCR_TYPE_MASK   0x00ff0000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_BCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DCR_TYPE_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DCR_TYPE_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DCR_TYPE_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DCR_TYPE_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC1_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x000002A4 )
 Register: XI3CPSX_DEV_CHAR_TABLE11_LOC2. More...
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_MSB_PROVISIONAL_ID_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_MSB_PROVISIONAL_ID_WIDTH   16
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_MSB_PROVISIONAL_ID_MASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC2_MSB_PROVISIONAL_ID_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x000002A8 )
 Register: XI3CPSX_DEV_CHAR_TABLE11_LOC3. More...
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_FULLMASK   0x0000ffff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_BCR_SHIFT   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_BCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_BCR_MASK   0x0000ff00
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_BCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_DCR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_DCR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_DCR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC3_DCR_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x000002AC )
 Register: XI3CPSX_DEV_CHAR_TABLE11_LOC4. More...
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_FULLMASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_FULLRWMASK   0x00000000
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_DEV_DYNAMIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_DEV_DYNAMIC_ADDR_MASK   0x000000ff
 
#define XI3CPSX_DEV_CHAR_TABLE11_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1   ( ( XI3CPSX_BASEADDR ) + 0x000002C0 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC1. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC1_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2   ( ( XI3CPSX_BASEADDR ) + 0x000002C4 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC2. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC2_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3   ( ( XI3CPSX_BASEADDR ) + 0x000002C8 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC3. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC3_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4   ( ( XI3CPSX_BASEADDR ) + 0x000002CC )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC4. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC4_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5   ( ( XI3CPSX_BASEADDR ) + 0x000002D0 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC5. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC5_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6   ( ( XI3CPSX_BASEADDR ) + 0x000002D4 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC6. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC6_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7   ( ( XI3CPSX_BASEADDR ) + 0x000002D8 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC7. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC7_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8   ( ( XI3CPSX_BASEADDR ) + 0x000002DC )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC8. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC8_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9   ( ( XI3CPSX_BASEADDR ) + 0x000002E0 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC9. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC9_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10   ( ( XI3CPSX_BASEADDR ) + 0x000002E4 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC10. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC10_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11   ( ( XI3CPSX_BASEADDR ) + 0x000002E8 )
 Register: XI3CPSX_DEV_ADDR_TABLE_LOC11. More...
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_FULLMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_FULLRWMASK   0xe0ff007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_LEGACY_I2C_DEVICE_SHIFT   31
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_LEGACY_I2C_DEVICE_WIDTH   1
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_LEGACY_I2C_DEVICE_MASK   0x80000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_LEGACY_I2C_DEVICE_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_NACK_RETRY_CNT_SHIFT   29
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_NACK_RETRY_CNT_WIDTH   2
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_NACK_RETRY_CNT_MASK   0x60000000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_NACK_RETRY_CNT_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_DYNAMIC_ADDR_SHIFT   16
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_DYNAMIC_ADDR_WIDTH   8
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_DYNAMIC_ADDR_MASK   0x00ff0000
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_DYNAMIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_STATIC_ADDR_SHIFT   0
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_STATIC_ADDR_MASK   0x0000007f
 
#define XI3CPSX_DEV_ADDR_TABLE_LOC11_DEV_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1   ( ( XI3CPSX_BASEADDR ) + 0x00004000 )
 Register: XI3CPSX_EXT_REG_1. More...
 
#define XI3CPSX_EXT_REG_1_FULLMASK   0x3fffffff
 
#define XI3CPSX_EXT_REG_1_FULLRWMASK   0x3feffffd
 
#define XI3CPSX_EXT_REG_1_DEFVAL   0x2
 
#define XI3CPSX_EXT_REG_1_SLV_CLK_DATA_TURN_TIME_SHIFT   27
 
#define XI3CPSX_EXT_REG_1_SLV_CLK_DATA_TURN_TIME_WIDTH   3
 
#define XI3CPSX_EXT_REG_1_SLV_CLK_DATA_TURN_TIME_MASK   0x38000000
 
#define XI3CPSX_EXT_REG_1_SLV_CLK_DATA_TURN_TIME_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_WR_SPEED_SHIFT   24
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_WR_SPEED_WIDTH   3
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_WR_SPEED_MASK   0x07000000
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_WR_SPEED_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_RD_SPEED_SHIFT   21
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_RD_SPEED_WIDTH   3
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_RD_SPEED_MASK   0x00e00000
 
#define XI3CPSX_EXT_REG_1_SLV_MAX_RD_SPEED_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_WAKEUP_SHIFT   20
 
#define XI3CPSX_EXT_REG_1_WAKEUP_WIDTH   1
 
#define XI3CPSX_EXT_REG_1_WAKEUP_MASK   0x00100000
 
#define XI3CPSX_EXT_REG_1_WAKEUP_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_INST_ID_SHIFT   16
 
#define XI3CPSX_EXT_REG_1_INST_ID_WIDTH   4
 
#define XI3CPSX_EXT_REG_1_INST_ID_MASK   0x000f0000
 
#define XI3CPSX_EXT_REG_1_INST_ID_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_SHIFT   9
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_WIDTH   7
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_MASK   0x0000fe00
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_EN_SHIFT   8
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_EN_WIDTH   1
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_EN_MASK   0x00000100
 
#define XI3CPSX_EXT_REG_1_STATIC_ADDR_EN_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_PENDING_INT_SHIFT   4
 
#define XI3CPSX_EXT_REG_1_PENDING_INT_WIDTH   4
 
#define XI3CPSX_EXT_REG_1_PENDING_INT_MASK   0x000000f0
 
#define XI3CPSX_EXT_REG_1_PENDING_INT_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_ACT_MODE_SHIFT   2
 
#define XI3CPSX_EXT_REG_1_ACT_MODE_WIDTH   2
 
#define XI3CPSX_EXT_REG_1_ACT_MODE_MASK   0x0000000c
 
#define XI3CPSX_EXT_REG_1_ACT_MODE_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_1_I2C_GLITCH_FILTER_EN_SHIFT   1
 
#define XI3CPSX_EXT_REG_1_I2C_GLITCH_FILTER_EN_WIDTH   1
 
#define XI3CPSX_EXT_REG_1_I2C_GLITCH_FILTER_EN_MASK   0x00000002
 
#define XI3CPSX_EXT_REG_1_I2C_GLITCH_FILTER_EN_DEFVAL   0x1
 
#define XI3CPSX_EXT_REG_1_MODE_I2C_SHIFT   0
 
#define XI3CPSX_EXT_REG_1_MODE_I2C_WIDTH   1
 
#define XI3CPSX_EXT_REG_1_MODE_I2C_MASK   0x00000001
 
#define XI3CPSX_EXT_REG_1_MODE_I2C_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_2   ( ( XI3CPSX_BASEADDR ) + 0x00004004 )
 Register: XI3CPSX_EXT_REG_2. More...
 
#define XI3CPSX_EXT_REG_2_FULLMASK   0xffffffff
 
#define XI3CPSX_EXT_REG_2_FULLRWMASK   0xffffffff
 
#define XI3CPSX_EXT_REG_2_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_2_SLV_PID_L_SHIFT   0
 
#define XI3CPSX_EXT_REG_2_SLV_PID_L_WIDTH   32
 
#define XI3CPSX_EXT_REG_2_SLV_PID_L_MASK   0xffffffff
 
#define XI3CPSX_EXT_REG_2_SLV_PID_L_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_3   ( ( XI3CPSX_BASEADDR ) + 0x00004008 )
 Register: XI3CPSX_EXT_REG_3. More...
 
#define XI3CPSX_EXT_REG_3_FULLMASK   0x00ffffff
 
#define XI3CPSX_EXT_REG_3_FULLRWMASK   0x00ffffff
 
#define XI3CPSX_EXT_REG_3_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_3_SLV_DCR_SHIFT   16
 
#define XI3CPSX_EXT_REG_3_SLV_DCR_WIDTH   8
 
#define XI3CPSX_EXT_REG_3_SLV_DCR_MASK   0x00ff0000
 
#define XI3CPSX_EXT_REG_3_SLV_DCR_DEFVAL   0x0
 
#define XI3CPSX_EXT_REG_3_SLV_PID_U_SHIFT   0
 
#define XI3CPSX_EXT_REG_3_SLV_PID_U_WIDTH   16
 
#define XI3CPSX_EXT_REG_3_SLV_PID_U_MASK   0x0000ffff
 
#define XI3CPSX_EXT_REG_3_SLV_PID_U_DEFVAL   0x0
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL   ( ( XI3CPSX_BASEADDR ) + 0x0000400C )
 Register: XI3CPSX_I3C_GLITCHFILTER_CTRL. More...
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_FULLMASK   0x0000003f
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_FULLRWMASK   0x0000003f
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_DEFVAL   0x10
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_GF_COUNTER_SHIFT   1
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_GF_COUNTER_WIDTH   5
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_GF_COUNTER_MASK   0x0000003e
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_GF_COUNTER_DEFVAL   0x8
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_USE_GF_SHIFT   0
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_USE_GF_WIDTH   1
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_USE_GF_MASK   0x00000001
 
#define XI3CPSX_I3C_GLITCHFILTER_CTRL_USE_GF_DEFVAL   0x0
 
#define XI3CPSX_ECO   ( ( XI3CPSX_BASEADDR ) + 0x00004010 )
 Register: XI3CPSX_ECO. More...
 
#define XI3CPSX_ECO_FULLMASK   0xffffffff
 
#define XI3CPSX_ECO_FULLRWMASK   0xffffffff
 
#define XI3CPSX_ECO_DEFVAL   0x0
 
#define XI3CPSX_ECO_FIELD_NAME_SHIFT   0
 
#define XI3CPSX_ECO_FIELD_NAME_WIDTH   32
 
#define XI3CPSX_ECO_FIELD_NAME_MASK   0xffffffff
 
#define XI3CPSX_ECO_FIELD_NAME_DEFVAL   0x0
 
#define XI3CPSX_EXT_DEBUG_REG_1   ( ( XI3CPSX_BASEADDR ) + 0x00004014 )
 Register: XI3CPSX_EXT_DEBUG_REG_1. More...
 
#define XI3CPSX_EXT_DEBUG_REG_1_FULLMASK   0xffffffff
 
#define XI3CPSX_EXT_DEBUG_REG_1_FULLRWMASK   0x00000000
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEFVAL   0x80005500
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_31_8_SHIFT   8
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_31_8_WIDTH   24
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_31_8_MASK   0xffffff00
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_31_8_DEFVAL   0x800055
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_7_0_SHIFT   0
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_7_0_WIDTH   8
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_7_0_MASK   0x000000ff
 
#define XI3CPSX_EXT_DEBUG_REG_1_DEBUG_PORT_7_0_DEFVAL   0x0
 
#define XI3CPSX_EXT_DEBUG_REG_2   ( ( XI3CPSX_BASEADDR ) + 0x00004018 )
 Register: XI3CPSX_EXT_DEBUG_REG_2. More...
 
#define XI3CPSX_EXT_DEBUG_REG_2_FULLMASK   0x0000ffff
 
#define XI3CPSX_EXT_DEBUG_REG_2_FULLRWMASK   0x00000000
 
#define XI3CPSX_EXT_DEBUG_REG_2_DEFVAL   0x0
 
#define XI3CPSX_EXT_DEBUG_REG_2_DEBUG_PORT_47_32_SHIFT   0
 
#define XI3CPSX_EXT_DEBUG_REG_2_DEBUG_PORT_47_32_WIDTH   16
 
#define XI3CPSX_EXT_DEBUG_REG_2_DEBUG_PORT_47_32_MASK   0x0000ffff
 
#define XI3CPSX_EXT_DEBUG_REG_2_DEBUG_PORT_47_32_DEFVAL   0x0