#include "xil_types.h"
#include "xil_assert.h"
#include "xstatus.h"
#include "xil_io.h"

Macros
#define	XIIC_READ_OPERATION 1
	The following constants are used to specify whether to do Read or a Write operation on IIC bus. More...

#define	XIIC_WRITE_OPERATION 0
	Write operation on the IIC bus. More...

#define	XIIC_MASTER_ROLE 1
	The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave. More...

#define	XIIC_SLAVE_ROLE 0
	Slave on the IIC bus. More...

#define	XIIC_STOP 0x00
	The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start. More...

#define	XIIC_REPEATED_START 0x01
	Do not Send a stop on the IIC bus after the current data transfer. More...

#define	XIic_ReadReg(BaseAddress, RegOffset) XIic_In32((BaseAddress) + (RegOffset))
	Read from the specified IIC device register. More...

#define	XIic_WriteReg(BaseAddress, RegOffset, RegisterValue) XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))
	Write to the specified IIC device register. More...

#define	XIic_IntrGlobalDisable(BaseAddress) XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, 0)
	This macro disables all interrupts for the device by writing to the Global interrupt enable register. More...

#define	XIic_IntrGlobalEnable(BaseAddress)
	This macro writes to the global interrupt enable register to enable interrupts from the device. More...

#define	XIic_IsIntrGlobalEnabled(BaseAddress)
	This function determines if interrupts are enabled at the global level by reading the global interrupt register. More...

#define	XIic_WriteIisr(BaseAddress, Status) XIic_WriteReg((BaseAddress), XIIC_IISR_OFFSET, (Status))
	This function sets the Interrupt status register to the specified value. More...

#define	XIic_ReadIisr(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IISR_OFFSET)
	This function gets the contents of the Interrupt Status Register. More...

#define	XIic_WriteIier(BaseAddress, Enable) XIic_WriteReg((BaseAddress), XIIC_IIER_OFFSET, (Enable))
	This function sets the contents of the Interrupt Enable Register. More...

#define	XIic_ReadIier(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IIER_OFFSET)
	This function gets the Interrupt Enable Register contents. More...

#define	XIic_ClearIisr(BaseAddress, InterruptMask)
	This macro clears the specified interrupt in the Interrupt status register. More...

#define	XIic_Send7BitAddress(BaseAddress, SlaveAddress, Operation)
	This macro sends the address for a 7 bit address during both read and write operations. More...

#define	XIic_DynSend7BitAddress(BaseAddress, SlaveAddress, Operation)
	This macro sends the address for a 7 bit address during both read and write operations. More...

#define	XIic_DynSendStartStopAddress(BaseAddress, SlaveAddress, Operation)
	This macro sends the address, start and stop for a 7 bit address during both write operations. More...

#define	XIic_DynSendStop(BaseAddress, ByteCount)
	This macro sends a stop condition on IIC bus for Dynamic logic. More...

Register Map
Register offsets for the XIic device.
#define	XIIC_DGIER_OFFSET 0x1C
	Global Interrupt Enable Register. More...

#define	XIIC_IISR_OFFSET 0x20
	Interrupt Status Register. More...

#define	XIIC_IIER_OFFSET 0x28
	Interrupt Enable Register. More...

#define	XIIC_RESETR_OFFSET 0x40
	Reset Register. More...

#define	XIIC_CR_REG_OFFSET 0x100
	Control Register. More...

#define	XIIC_SR_REG_OFFSET 0x104
	Status Register. More...

#define	XIIC_DTR_REG_OFFSET 0x108
	Data Tx Register. More...

#define	XIIC_DRR_REG_OFFSET 0x10C
	Data Rx Register. More...

#define	XIIC_ADR_REG_OFFSET 0x110
	Address Register. More...

#define	XIIC_TFO_REG_OFFSET 0x114
	Tx FIFO Occupancy. More...

#define	XIIC_RFO_REG_OFFSET 0x118
	Rx FIFO Occupancy. More...

#define	XIIC_TBA_REG_OFFSET 0x11C
	10 Bit Address reg More...

#define	XIIC_RFD_REG_OFFSET 0x120
	Rx FIFO Depth reg. More...

#define	XIIC_GPO_REG_OFFSET 0x124
	Output Register. More...

Device Global Interrupt Enable Register masks (CR) mask(s)
#define	XIIC_GINTR_ENABLE_MASK 0x80000000
	Global Interrupt Enable Mask. More...

IIC Device Interrupt Status/Enable (INTR) Register Masks
Interrupt Status Register (IISR) This register holds the interrupt status flags for the Spi device. Interrupt Enable Register (IIER) This register is used to enable interrupt sources for the IIC device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt. IISR/IIER registers have the same bit definitions and are only defined once.
#define	XIIC_INTR_ARB_LOST_MASK 0x00000001
	1 = Arbitration lost More...

#define	XIIC_INTR_TX_ERROR_MASK 0x00000002
	1 = Tx error/msg complete More...

#define	XIIC_INTR_TX_EMPTY_MASK 0x00000004
	1 = Tx FIFO/reg empty More...

#define	XIIC_INTR_RX_FULL_MASK 0x00000008
	1 = Rx FIFO/reg=OCY level More...

#define	XIIC_INTR_BNB_MASK 0x00000010
	1 = Bus not busy More...

#define	XIIC_INTR_AAS_MASK 0x00000020
	1 = When addr as slave More...

#define	XIIC_INTR_NAAS_MASK 0x00000040
	1 = Not addr as slave More...

#define	XIIC_INTR_TX_HALF_MASK 0x00000080
	1 = Tx FIFO half empty More...

#define	XIIC_TX_INTERRUPTS
	All Tx interrupts commonly used. More...

#define	XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK \| XIIC_TX_INTERRUPTS)
	All interrupts commonly used. More...

Reset Register mask
#define	XIIC_RESET_MASK 0x0000000A
	RESET Mask. More...

Control Register masks (CR) mask(s)
#define	XIIC_CR_ENABLE_DEVICE_MASK 0x00000001
	Device enable = 1. More...

#define	XIIC_CR_TX_FIFO_RESET_MASK 0x00000002
	Transmit FIFO reset=1. More...

#define	XIIC_CR_MSMS_MASK 0x00000004
	Master starts Txing=1. More...

#define	XIIC_CR_DIR_IS_TX_MASK 0x00000008
	Dir of Tx. More...

#define	XIIC_CR_NO_ACK_MASK 0x00000010
	Tx Ack. More...

#define	XIIC_CR_REPEATED_START_MASK 0x00000020
	Repeated start = 1. More...

#define	XIIC_CR_GENERAL_CALL_MASK 0x00000040
	Gen Call enabled = 1. More...

Status Register masks (SR) mask(s)
#define	XIIC_SR_GEN_CALL_MASK 0x00000001
	1 = A Master issued a GC More...

#define	XIIC_SR_ADDR_AS_SLAVE_MASK 0x00000002
	1 = When addressed as slave More...

#define	XIIC_SR_BUS_BUSY_MASK 0x00000004
	1 = Bus is busy More...

#define	XIIC_SR_MSTR_RDING_SLAVE_MASK 0x00000008
	1 = Dir: Master <– slave More...

#define	XIIC_SR_TX_FIFO_FULL_MASK 0x00000010
	1 = Tx FIFO full More...

#define	XIIC_SR_RX_FIFO_FULL_MASK 0x00000020
	1 = Rx FIFO full More...

#define	XIIC_SR_RX_FIFO_EMPTY_MASK 0x00000040
	1 = Rx FIFO empty More...

#define	XIIC_SR_TX_FIFO_EMPTY_MASK 0x00000080
	1 = Tx FIFO empty More...

Data Tx Register (DTR) mask(s)
#define	XIIC_TX_DYN_START_MASK 0x00000100
	1 = Set dynamic start More...

#define	XIIC_TX_DYN_STOP_MASK 0x00000200
	1 = Set dynamic stop More...

#define	IIC_TX_FIFO_DEPTH 16
	Tx fifo capacity. More...

Data Rx Register (DRR) mask(s)
#define	IIC_RX_FIFO_DEPTH 16
	Rx fifo capacity. More...

Functions
unsigned	XIic_Recv (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
	Receive data as a master on the IIC bus. More...

unsigned	XIic_Send (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option)
	Send data as a master on the IIC bus. More...

unsigned	XIic_DynRecv (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount)
	Receive data as a master on the IIC bus. More...

unsigned	XIic_DynSend (UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option)
	Send data as a master on the IIC bus. More...

u32	XIic_WaitBusFree (UINTPTR BaseAddress)
	This function will wait until the I2C bus is free or timeout. More...

Macro Definition Documentation

#define IIC_RX_FIFO_DEPTH 16

Rx fifo capacity.

Referenced by XIic_DynMasterRecv(), XIic_MasterRecv(), and XIic_SlaveRecv().

#define IIC_TX_FIFO_DEPTH 16

Tx fifo capacity.

#define XIic_ClearIisr	(	BaseAddress,
		InterruptMask
	)

Value:

XIic_WriteIisr((BaseAddress), \

XIic_ReadIisr(BaseAddress) & (InterruptMask))

XIic_ReadIisr

#define XIic_ReadIisr(BaseAddress)

This function gets the contents of the Interrupt Status Register.

Definition: xiic_l.h:402

XIic_WriteIisr

#define XIic_WriteIisr(BaseAddress, Status)

This function sets the Interrupt status register to the specified value.

Definition: xiic_l.h:383

This macro clears the specified interrupt in the Interrupt status register.

It is non-destructive in that the register is read and only the interrupt specified is cleared. Clearing an interrupt acknowledges it.

Parameters

BaseAddress	is the base address of the IIC device.
InterruptMask	is the bit mask of the interrupts to be cleared.

Returns: None.

Note: C-Style signature: void XIic_ClearIisr(u32 BaseAddress, u32 InterruptMask);

Referenced by XIic_DynRecv(), XIic_DynSend(), XIic_Recv(), and XIic_Send().

#define XIIC_CR_DIR_IS_TX_MASK 0x00000008

Dir of Tx.

Txing=1

Referenced by XIic_DynMasterSend(), XIic_MasterSend(), XIic_Recv(), and XIic_Send().

#define XIIC_CR_ENABLE_DEVICE_MASK 0x00000001

Device enable = 1.

Referenced by EepromReadByte(), EepromWriteByte(), XIic_Recv(), XIic_Send(), and XIic_Start().

#define XIIC_CR_GENERAL_CALL_MASK 0x00000040

Gen Call enabled = 1.

Referenced by XIic_SetOptions().

#define XIIC_CR_MSMS_MASK 0x00000004

Master starts Txing=1.

Referenced by XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Recv(), XIic_Send(), and XIic_Stop().

#define XIIC_CR_NO_ACK_MASK 0x00000010

Tx Ack.

NO ack = 1

Referenced by XIic_DynMasterSend(), XIic_MasterSend(), and XIic_Recv().

#define XIIC_CR_REPEATED_START_MASK 0x00000020

Repeated start = 1.

Referenced by XIic_DynMasterRecv(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Recv(), and XIic_Send().

#define XIIC_CR_TX_FIFO_RESET_MASK 0x00000002

Transmit FIFO reset=1.

Referenced by EepromReadByte(), and EepromWriteByte().

#define XIic_DynSend7BitAddress	(	BaseAddress,
		SlaveAddress,
		Operation
	)

Value:

{                                                                       \
        u8 LocalAddr = (u8)(SlaveAddress << 1);                         \
        LocalAddr = (LocalAddr & 0xFE) | (Operation);                   \
	XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                \
                        XIIC_TX_DYN_START_MASK | LocalAddr);            \
}

This macro sends the address for a 7 bit address during both read and write operations.

It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers for Dynamic controller functionality.

Parameters

BaseAddress	is the base address of the IIC Device.
SlaveAddress	is the address of the slave to send to.
Operation	indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION.

Returns: None.

Note: C-Style signature: void XIic_DynSend7BitAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation);

Referenced by XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_DynRecv(), and XIic_DynSend().

#define XIic_DynSendStartStopAddress	(	BaseAddress,
		SlaveAddress,
		Operation
	)

Value:

{                                                                        \
        u8 LocalAddr = (u8)(SlaveAddress << 1);                          \
        LocalAddr = (LocalAddr & 0xFE) | (Operation);                    \
	XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                 \
                        XIIC_TX_DYN_START_MASK | XIIC_TX_DYN_STOP_MASK | \
                        LocalAddr);                                      \
}

This macro sends the address, start and stop for a 7 bit address during both write operations.

It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers.

Parameters

BaseAddress	is the base address of the IIC Device.
SlaveAddress	is the address of the slave to send to.
Operation	indicates XIIC_WRITE_OPERATION.

Returns: None.

Note: C-Style signature: void XIic_DynSendStartStopAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation);

Referenced by XIic_DynSend().

#define XIic_DynSendStop	(	BaseAddress,
		ByteCount
	)

Value:

{                                                                       \
	XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET,                \
                        XIIC_TX_DYN_STOP_MASK | ByteCount);             \
}

This macro sends a stop condition on IIC bus for Dynamic logic.

Parameters

BaseAddress	is the base address of the IIC Device.
ByteCount	is the number of Rx bytes received before the master. doesn't respond with ACK.

Returns: None.

Note: C-Style signature: void XIic_DynSendStop(u32 BaseAddress, u32 ByteCount);

Referenced by XIic_DynMasterRecv(), and XIic_DynRecv().

#define XIIC_GINTR_ENABLE_MASK 0x80000000

Global Interrupt Enable Mask.

#define XIIC_INTR_AAS_MASK 0x00000020

1 = When addr as slave

Referenced by XIic_InterruptHandler(), and XIic_Start().

#define XIIC_INTR_ARB_LOST_MASK 0x00000001

1 = Arbitration lost

Referenced by XIic_DynRecv(), XIic_DynSend(), XIic_InterruptHandler(), XIic_Recv(), XIic_Send(), and XIic_Start().

#define XIIC_INTR_BNB_MASK 0x00000010

1 = Bus not busy

Referenced by XIic_DynRecv(), XIic_DynSend(), XIic_InterruptHandler(), XIic_Recv(), and XIic_Send().

#define XIIC_INTR_NAAS_MASK 0x00000040

1 = Not addr as slave

Referenced by XIic_InterruptHandler().

#define XIIC_INTR_RX_FULL_MASK 0x00000008

1 = Rx FIFO/reg=OCY level

Referenced by XIic_DynMasterRecv(), XIic_InterruptHandler(), XIic_MasterRecv(), XIic_Recv(), and XIic_SlaveRecv().

#define XIIC_INTR_TX_EMPTY_MASK 0x00000004

1 = Tx FIFO/reg empty

Referenced by XIic_DynMasterSend(), XIic_DynRecv(), XIic_DynSend(), XIic_InterruptHandler(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Send(), and XIic_SlaveSend().

#define XIIC_INTR_TX_ERROR_MASK 0x00000002

1 = Tx error/msg complete

Referenced by XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_DynRecv(), XIic_DynSend(), XIic_InterruptHandler(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Recv(), XIic_Send(), and XIic_SlaveSend().

#define XIIC_INTR_TX_HALF_MASK 0x00000080

1 = Tx FIFO half empty

Referenced by XIic_DynMasterSend(), XIic_InterruptHandler(), XIic_MasterSend(), and XIic_SlaveSend().

#define XIic_IntrGlobalDisable ( BaseAddress ) XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, 0)

This macro disables all interrupts for the device by writing to the Global interrupt enable register.

Parameters

BaseAddress is the base address of the IIC device.

Returns: None.

Note: C-Style signature: void XIic_IntrGlobalDisable(u32 BaseAddress);

Referenced by SlaveReadData(), SlaveWriteData(), TenBitAddrReadData(), TenBitAddrWriteData(), XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_MasterRecv(), XIic_MasterSend(), XIic_SetOptions(), XIic_SlaveRecv(), XIic_SlaveSend(), and XIic_Stop().

#define XIic_IntrGlobalEnable ( BaseAddress )

Value:

XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, \

XIIC_GINTR_ENABLE_MASK)

XIic_WriteReg

#define XIic_WriteReg(BaseAddress, RegOffset, RegisterValue)

Write to the specified IIC device register.

Definition: xiic_l.h:299

XIIC_DGIER_OFFSET

#define XIIC_DGIER_OFFSET

Global Interrupt Enable Register.

Definition: xiic_l.h:87

XIIC_GINTR_ENABLE_MASK

#define XIIC_GINTR_ENABLE_MASK

Global Interrupt Enable Mask.

Definition: xiic_l.h:123

This macro writes to the global interrupt enable register to enable interrupts from the device.

This function does not enable individual interrupts as the Interrupt Enable Register must be set appropriately.

Parameters

BaseAddress is the base address of the IIC device.

Returns: None.

Note: C-Style signature: void XIic_IntrGlobalEnable(u32 BaseAddress);

Referenced by IicPmbusInterruptSdtExample(), SlaveReadData(), SlaveWriteData(), TenBitAddrReadData(), TenBitAddrWriteData(), XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_MasterRecv(), XIic_MasterSend(), XIic_SelfTest(), XIic_SetOptions(), XIic_SlaveRecv(), XIic_SlaveSend(), XIic_Start(), and XIic_Stop().

#define XIic_IsIntrGlobalEnabled ( BaseAddress )

Value:

(XIic_ReadReg((BaseAddress), XIIC_DGIER_OFFSET) == \

XIIC_GINTR_ENABLE_MASK)

XIIC_DGIER_OFFSET

#define XIIC_DGIER_OFFSET

Global Interrupt Enable Register.

Definition: xiic_l.h:87

XIic_ReadReg

#define XIic_ReadReg(BaseAddress, RegOffset)

Read from the specified IIC device register.

Definition: xiic_l.h:276

XIIC_GINTR_ENABLE_MASK

#define XIIC_GINTR_ENABLE_MASK

Global Interrupt Enable Mask.

Definition: xiic_l.h:123

This function determines if interrupts are enabled at the global level by reading the global interrupt register.

Parameters

BaseAddress is the base address of the IIC device.

Returns

TRUE if the global interrupt is enabled.
FALSE if global interrupt is disabled.

Note: C-Style signature: int XIic_IsIntrGlobalEnabled(u32 BaseAddress);

Referenced by XIic_InterruptHandler(), and XIic_SelfTest().

#define XIIC_MASTER_ROLE 1

The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave.

Master on the IIC bus

Referenced by XIic_DynMasterSend(), and XIic_MasterSend().

#define XIIC_READ_OPERATION 1

The following constants are used to specify whether to do Read or a Write operation on IIC bus.

Read operation on the IIC bus

Referenced by XIic_DynMasterRecv(), XIic_DynRecv(), XIic_MasterRecv(), and XIic_Recv().

#define XIic_ReadIier ( BaseAddress ) XIic_ReadReg((BaseAddress), XIIC_IIER_OFFSET)

This function gets the Interrupt Enable Register contents.

Parameters

BaseAddress is the base address of the IIC device.

Returns: The contents read from the Interrupt Enable Register. Bit positions of 1 indicate that the corresponding interrupt is enabled. Bit positions of 0 indicate that the corresponding interrupt is disabled.

Note: C-Style signature: u32 XIic_ReadIier(u32 BaseAddress)

Referenced by XIic_InterruptHandler(), and XIic_SelfTest().

#define XIic_ReadIisr ( BaseAddress ) XIic_ReadReg((BaseAddress), XIIC_IISR_OFFSET)

This function gets the contents of the Interrupt Status Register.

This register indicates the status of interrupt sources for the device. The status is independent of whether interrupts are enabled such that the status register may also be polled when interrupts are not enabled.

Parameters

BaseAddress is the base address of the IIC device.

Returns: The value read from the Interrupt Status Register.

Note: C-Style signature: u32 XIic_ReadIisr(u32 BaseAddress);

Referenced by XIic_InterruptHandler().

#define XIic_ReadReg	(	BaseAddress,
		RegOffset
	)	XIic_In32((BaseAddress) + (RegOffset))

Read from the specified IIC device register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the offset from the 1st register of the device to select the specific register.

Returns: The value read from the register.

Note

C-Style signature: u32 XIic_ReadReg(u32 BaseAddress, u32 RegOffset);

    This macro does not do any checking to ensure that the

register exists if the register may be excluded due to parameterization, such as the GPO Register.

Referenced by EepromReadByte(), EepromWriteByte(), IicLowLevelDynEeprom(), XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_DynRecv(), XIic_DynSend(), XIic_GetAddress(), XIic_GetGpOutput(), XIic_InterruptHandler(), XIic_IsSlave(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Recv(), XIic_Send(), XIic_SetClk(), XIic_SetOptions(), XIic_SlaveRecv(), XIic_SlaveSend(), and XIic_Stop().

#define XIIC_REPEATED_START 0x01

Do not Send a stop on the IIC bus after the current data transfer.

Referenced by EepromReadByte().

#define XIIC_RESET_MASK 0x0000000A

RESET Mask.

Referenced by XIic_Reset().

#define XIic_Send7BitAddress	(	BaseAddress,
		SlaveAddress,
		Operation
	)

Value:

{                                                                       \
        u8 LocalAddr = (u8)(SlaveAddress << 1);                         \
        LocalAddr = (LocalAddr & 0xFE) | (Operation);                   \
	XIic_WriteReg(BaseAddress, XIIC_DTR_REG_OFFSET, LocalAddr);    \
}

This macro sends the address for a 7 bit address during both read and write operations.

It takes care of the details to format the address correctly. This macro is designed to be called internally to the drivers.

Parameters

BaseAddress	is the base address of the IIC Device.
SlaveAddress	is the address of the slave to send to.
Operation	indicates XIIC_READ_OPERATION or XIIC_WRITE_OPERATION

Returns: None.

Note: C-Style signature: void XIic_Send7BitAddress(u32 BaseAddress, u8 SlaveAddress, u8 Operation);

Referenced by XIic_Recv(), and XIic_Send().

#define XIIC_SLAVE_ROLE 0

Slave on the IIC bus.

Referenced by XIic_SlaveSend().

#define XIIC_SR_ADDR_AS_SLAVE_MASK 0x00000002

1 = When addressed as slave

Referenced by XIic_InterruptHandler(), XIic_IsSlave(), XIic_Send(), XIic_SlaveRecv(), XIic_SlaveSend(), and XIic_Stop().

#define XIIC_SR_BUS_BUSY_MASK 0x00000004

1 = Bus is busy

Referenced by EepromReadByte(), IicLowLevelDynEeprom(), XIic_DynRecv(), XIic_DynSend(), XIic_Recv(), and XIic_Send().

#define XIIC_SR_GEN_CALL_MASK 0x00000001

1 = A Master issued a GC

#define XIIC_SR_MSTR_RDING_SLAVE_MASK 0x00000008

1 = Dir: Master <– slave

#define XIIC_SR_RX_FIFO_EMPTY_MASK 0x00000040

1 = Rx FIFO empty

Referenced by IicLowLevelDynEeprom().

#define XIIC_SR_RX_FIFO_FULL_MASK 0x00000020

1 = Rx FIFO full

#define XIIC_SR_TX_FIFO_EMPTY_MASK 0x00000080

1 = Tx FIFO empty

Referenced by IicLowLevelDynEeprom().

#define XIIC_SR_TX_FIFO_FULL_MASK 0x00000010

1 = Tx FIFO full

#define XIIC_STOP 0x00

The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start.

Send a stop on the IIC bus after the current data transfer

Referenced by EepromReadByte(), EepromWriteByte(), and LowLevelTempSensorExample().

#define XIIC_TX_DYN_START_MASK 0x00000100

1 = Set dynamic start

#define XIIC_TX_DYN_STOP_MASK 0x00000200

1 = Set dynamic stop

Referenced by XIic_DynSend().

#define XIIC_TX_INTERRUPTS

Value:

(XIIC_INTR_TX_ERROR_MASK | \
				 XIIC_INTR_TX_EMPTY_MASK |  \
				 XIIC_INTR_TX_HALF_MASK)

All Tx interrupts commonly used.

#define XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS)

All interrupts commonly used.

Referenced by XIic_SelfTest().

#define XIIC_WRITE_OPERATION 0

Write operation on the IIC bus.

Referenced by XIic_DynMasterSend(), XIic_DynSend(), XIic_MasterRecv(), XIic_MasterSend(), and XIic_Send().

#define XIic_WriteIier	(	BaseAddress,
		Enable
	)	XIic_WriteReg((BaseAddress), XIIC_IIER_OFFSET, (Enable))

This function sets the contents of the Interrupt Enable Register.

This function writes only the specified value to the register such that some interrupt sources may be enabled and others disabled. It is the caller's responsibility to get the value of the interrupt enable register prior to setting the value to prevent a destructive behavior.

Parameters

BaseAddress	is the base address of the IIC device.
Enable	is the value to be written to the Interrupt Enable Register. Bit positions of 1 will be enabled. Bit positions of 0 will be disabled.

Returns: None

Note: C-Style signature: void XIic_WriteIier(u32 BaseAddress, u32 Enable);

Referenced by XIic_SelfTest(), and XIic_Start().

#define XIic_WriteIisr	(	BaseAddress,
		Status
	)	XIic_WriteReg((BaseAddress), XIIC_IISR_OFFSET, (Status))

This function sets the Interrupt status register to the specified value.

This register implements a toggle on write functionality. The interrupt is cleared by writing to this register with the bits to be cleared set to a one and all others to zero. Setting a bit which is zero within this register causes an interrupt to be generated.

This function writes only the specified value to the register such that some status bits may be set and others cleared. It is the caller's responsibility to get the value of the register prior to setting the value to prevent an destructive behavior.

Parameters

BaseAddress	is the base address of the IIC device.
Status	is the value to be written to the Interrupt status register.

Returns: None.

Note: C-Style signature: void XIic_WriteIisr(u32 BaseAddress, u32 Status);

Referenced by XIic_InterruptHandler().

#define XIic_WriteReg	(	BaseAddress,
		RegOffset,
		RegisterValue
	)	XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue))

Write to the specified IIC device register.

Parameters

BaseAddress	is the base address of the device.
RegOffset	is the offset from the 1st register of the device to select the specific register.
RegisterValue	is the value to be written to the register.

Returns: None.

Note: C-Style signature: void XIic_WriteReg(u32 BaseAddress, u32 RegOffset, u32 RegisterValue); This macro does not do any checking to ensure that the register exists if the register may be excluded due to parameterization, such as the GPO Register.

Referenced by EepromReadByte(), EepromWriteByte(), XIic_DynMasterRecv(), XIic_DynMasterSend(), XIic_MasterRecv(), XIic_MasterSend(), XIic_Recv(), XIic_Reset(), XIic_Send(), XIic_SetAddress(), XIic_SetGpOutput(), XIic_SetOptions(), XIic_SlaveRecv(), and XIic_Start().

Macros

Functions

Macro Definition Documentation