 |
iic
Vitis Drivers API Documentation
|
|
iic
Vitis Drivers API Documentation
|
Macros | |
| #define | XIIC_READ_OPERATION 1 |
| The following constants are used to specify whether to do Read or a Write operation on IIC bus. More... | |
| #define | XIIC_WRITE_OPERATION 0 |
| Write operation on the IIC bus. More... | |
| #define | XIIC_MASTER_ROLE 1 |
| The following constants are used with the transmit FIFO fill function to specify the role which the IIC device is acting as, a master or a slave. More... | |
| #define | XIIC_SLAVE_ROLE 0 |
| Slave on the IIC bus. More... | |
| #define | XIIC_STOP 0x00 |
| The following constants are used with Transmit Function (XIic_Send) to specify whether to STOP after the current transfer of data or own the bus with a Repeated start. More... | |
| #define | XIIC_REPEATED_START 0x01 |
| Donot Send a stop on the IIC bus after the current data transfer. More... | |
| #define | XIic_ReadReg(BaseAddress, RegOffset) XIic_In32((BaseAddress) + (RegOffset)) |
| Read from the specified IIC device register. More... | |
| #define | XIic_WriteReg(BaseAddress, RegOffset, RegisterValue) XIic_Out32((BaseAddress) + (RegOffset), (RegisterValue)) |
| Write to the specified IIC device register. More... | |
| #define | XIic_IntrGlobalDisable(BaseAddress) XIic_WriteReg((BaseAddress), XIIC_DGIER_OFFSET, 0) |
| This macro disables all interrupts for the device by writing to the Global interrupt enable register. More... | |
| #define | XIic_IntrGlobalEnable(BaseAddress) |
| This macro writes to the global interrupt enable register to enable interrupts from the device. More... | |
| #define | XIic_IsIntrGlobalEnabled(BaseAddress) |
| This function determines if interrupts are enabled at the global level by reading the global interrupt register. More... | |
| #define | XIic_WriteIisr(BaseAddress, Status) XIic_WriteReg((BaseAddress), XIIC_IISR_OFFSET, (Status)) |
| This function sets the Interrupt status register to the specified value. More... | |
| #define | XIic_ReadIisr(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IISR_OFFSET) |
| This function gets the contents of the Interrupt Status Register. More... | |
| #define | XIic_WriteIier(BaseAddress, Enable) XIic_WriteReg((BaseAddress), XIIC_IIER_OFFSET, (Enable)) |
| This function sets the contents of the Interrupt Enable Register. More... | |
| #define | XIic_ReadIier(BaseAddress) XIic_ReadReg((BaseAddress), XIIC_IIER_OFFSET) |
| This function gets the Interrupt Enable Register contents. More... | |
| #define | XIic_ClearIisr(BaseAddress, InterruptMask) |
| This macro clears the specified interrupt in the Interrupt status register. More... | |
| #define | XIic_Send7BitAddress(BaseAddress, SlaveAddress, Operation) |
| This macro sends the address for a 7 bit address during both read and write operations. More... | |
| #define | XIic_DynSend7BitAddress(BaseAddress, SlaveAddress, Operation) |
| This macro sends the address for a 7 bit address during both read and write operations. More... | |
| #define | XIic_DynSendStartStopAddress(BaseAddress, SlaveAddress, Operation) |
| This macro sends the address, start and stop for a 7 bit address during both write operations. More... | |
| #define | XIic_DynSendStop(BaseAddress, ByteCount) |
| This macro sends a stop condition on IIC bus for Dynamic logic. More... | |
Register Map | |
Register offsets for the XIic device. | |
| #define | XIIC_DGIER_OFFSET 0x1C |
| Global Interrupt Enable Register. More... | |
| #define | XIIC_IISR_OFFSET 0x20 |
| Interrupt Status Register. More... | |
| #define | XIIC_IIER_OFFSET 0x28 |
| Interrupt Enable Register. More... | |
| #define | XIIC_RESETR_OFFSET 0x40 |
| Reset Register. More... | |
| #define | XIIC_CR_REG_OFFSET 0x100 |
| Control Register. More... | |
| #define | XIIC_SR_REG_OFFSET 0x104 |
| Status Register. More... | |
| #define | XIIC_DTR_REG_OFFSET 0x108 |
| Data Tx Register. More... | |
| #define | XIIC_DRR_REG_OFFSET 0x10C |
| Data Rx Register. More... | |
| #define | XIIC_ADR_REG_OFFSET 0x110 |
| Address Register. More... | |
| #define | XIIC_TFO_REG_OFFSET 0x114 |
| Tx FIFO Occupancy. More... | |
| #define | XIIC_RFO_REG_OFFSET 0x118 |
| Rx FIFO Occupancy. More... | |
| #define | XIIC_TBA_REG_OFFSET 0x11C |
| 10 Bit Address reg More... | |
| #define | XIIC_RFD_REG_OFFSET 0x120 |
| Rx FIFO Depth reg. More... | |
| #define | XIIC_GPO_REG_OFFSET 0x124 |
| Output Register. More... | |
Device Global Interrupt Enable Register masks (CR) mask(s) | |
| #define | XIIC_GINTR_ENABLE_MASK 0x80000000 |
| Global Interrupt Enable Mask. More... | |
IIC Device Interrupt Status/Enable (INTR) Register Masks | |
Interrupt Status Register (IISR) This register holds the interrupt status flags for the Spi device. Interrupt Enable Register (IIER) This register is used to enable interrupt sources for the IIC device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt. IISR/IIER registers have the same bit definitions and are only defined once. | |
| #define | XIIC_INTR_ARB_LOST_MASK 0x00000001 |
| 1 = Arbitration lost More... | |
| #define | XIIC_INTR_TX_ERROR_MASK 0x00000002 |
| 1 = Tx error/msg complete More... | |
| #define | XIIC_INTR_TX_EMPTY_MASK 0x00000004 |
| 1 = Tx FIFO/reg empty More... | |
| #define | XIIC_INTR_RX_FULL_MASK 0x00000008 |
| 1 = Rx FIFO/reg=OCY level More... | |
| #define | XIIC_INTR_BNB_MASK 0x00000010 |
| 1 = Bus not busy More... | |
| #define | XIIC_INTR_AAS_MASK 0x00000020 |
| 1 = When addr as slave More... | |
| #define | XIIC_INTR_NAAS_MASK 0x00000040 |
| 1 = Not addr as slave More... | |
| #define | XIIC_INTR_TX_HALF_MASK 0x00000080 |
| 1 = Tx FIFO half empty More... | |
| #define | XIIC_TX_INTERRUPTS |
| All Tx interrupts commonly used. More... | |
| #define | XIIC_TX_RX_INTERRUPTS (XIIC_INTR_RX_FULL_MASK | XIIC_TX_INTERRUPTS) |
| All interrupts commonly used. More... | |
Reset Register mask | |
| #define | XIIC_RESET_MASK 0x0000000A |
| RESET Mask. More... | |
Control Register masks (CR) mask(s) | |
| #define | XIIC_CR_ENABLE_DEVICE_MASK 0x00000001 |
| Device enable = 1. More... | |
| #define | XIIC_CR_TX_FIFO_RESET_MASK 0x00000002 |
| Transmit FIFO reset=1. More... | |
| #define | XIIC_CR_MSMS_MASK 0x00000004 |
| Master starts Txing=1. More... | |
| #define | XIIC_CR_DIR_IS_TX_MASK 0x00000008 |
| Dir of Tx. More... | |
| #define | XIIC_CR_NO_ACK_MASK 0x00000010 |
| Tx Ack. More... | |
| #define | XIIC_CR_REPEATED_START_MASK 0x00000020 |
| Repeated start = 1. More... | |
| #define | XIIC_CR_GENERAL_CALL_MASK 0x00000040 |
| Gen Call enabled = 1. More... | |
Status Register masks (SR) mask(s) | |
| #define | XIIC_SR_GEN_CALL_MASK 0x00000001 |
| 1 = A Master issued a GC More... | |
| #define | XIIC_SR_ADDR_AS_SLAVE_MASK 0x00000002 |
| 1 = When addressed as slave More... | |
| #define | XIIC_SR_BUS_BUSY_MASK 0x00000004 |
| 1 = Bus is busy More... | |
| #define | XIIC_SR_MSTR_RDING_SLAVE_MASK 0x00000008 |
| 1 = Dir: Master <– slave More... | |
| #define | XIIC_SR_TX_FIFO_FULL_MASK 0x00000010 |
| 1 = Tx FIFO full More... | |
| #define | XIIC_SR_RX_FIFO_FULL_MASK 0x00000020 |
| 1 = Rx FIFO full More... | |
| #define | XIIC_SR_RX_FIFO_EMPTY_MASK 0x00000040 |
| 1 = Rx FIFO empty More... | |
| #define | XIIC_SR_TX_FIFO_EMPTY_MASK 0x00000080 |
| 1 = Tx FIFO empty More... | |
Data Tx Register (DTR) mask(s) | |
| #define | XIIC_TX_DYN_START_MASK 0x00000100 |
| 1 = Set dynamic start More... | |
| #define | XIIC_TX_DYN_STOP_MASK 0x00000200 |
| 1 = Set dynamic stop More... | |
| #define | IIC_TX_FIFO_DEPTH 16 |
| Tx fifo capacity. More... | |
Data Rx Register (DRR) mask(s) | |
| #define | IIC_RX_FIFO_DEPTH 16 |
| Rx fifo capacity. More... | |
Functions | |
| unsigned | XIic_Recv (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option) |
| Receive data as a master on the IIC bus. More... | |
| unsigned | XIic_Send (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, unsigned ByteCount, u8 Option) |
| Send data as a master on the IIC bus. More... | |
| unsigned | XIic_DynRecv (UINTPTR BaseAddress, u8 Address, u8 *BufferPtr, u8 ByteCount) |
| Receive data as a master on the IIC bus. More... | |
| unsigned | XIic_DynSend (UINTPTR BaseAddress, u16 Address, u8 *BufferPtr, u8 ByteCount, u8 Option) |
| Send data as a master on the IIC bus. More... | |
| u32 | XIic_WaitBusFree (UINTPTR BaseAddress) |
| This function will wait until the I2C bus is free or timeout. More... | |