Macros
#define	XIICPS_HW_H
	by using protection macros More...

#define	XIicPs_ReadReg(BaseAddress, RegOffset) XIicPs_In32((BaseAddress) + (u32)(RegOffset))
	Read an IIC register. More...

#define	XIicPs_WriteReg(BaseAddress, RegOffset, RegisterValue) XIicPs_Out32((BaseAddress) + (u32)(RegOffset), (u32)(RegisterValue))
	Write an IIC register. More...

#define	XIicPs_ReadIER(BaseAddress) XIicPs_ReadReg((BaseAddress), XIICPS_IER_OFFSET)
	Read the interrupt enable register. More...

#define	XIicPs_EnableInterrupts(BaseAddress, IntrMask) XIicPs_WriteReg((BaseAddress), XIICPS_IER_OFFSET, (IntrMask))
	Write to the interrupt enable register. More...

#define	XIicPs_DisableAllInterrupts(BaseAddress)
	Disable all interrupts. More...

#define	XIicPs_DisableInterrupts(BaseAddress, IntrMask)
	Disable selected interrupts. More...

Register Map
Register offsets for the IIC.
#define	XIICPS_CR_OFFSET 0x00U
	32-bit Control More...

#define	XIICPS_SR_OFFSET 0x04U
	Status. More...

#define	XIICPS_ADDR_OFFSET 0x08U
	IIC Address. More...

#define	XIICPS_DATA_OFFSET 0x0CU
	IIC FIFO Data. More...

#define	XIICPS_ISR_OFFSET 0x10U
	Interrupt Status. More...

#define	XIICPS_TRANS_SIZE_OFFSET 0x14U
	Transfer Size. More...

#define	XIICPS_SLV_PAUSE_OFFSET 0x18U
	Slave monitor pause. More...

#define	XIICPS_TIME_OUT_OFFSET 0x1CU
	Time Out. More...

#define	XIICPS_IMR_OFFSET 0x20U
	Interrupt Enabled Mask. More...

#define	XIICPS_IER_OFFSET 0x24U
	Interrupt Enable. More...

#define	XIICPS_IDR_OFFSET 0x28U
	Interrupt Disable. More...

IIC Interrupt Registers
IIC Interrupt Status Register This register holds the interrupt status flags for the IIC controller. Some of the flags are level triggered i.e. are set as long as the interrupt condition exists. Other flags are edge triggered, which means they are set one the interrupt condition occurs then remain set until they are cleared by software. The interrupts are cleared by writing a one to the interrupt bit position in the Interrupt Status Register. Read/Write. IIC Interrupt Enable Register This register is used to enable interrupt sources for the IIC controller. Writing a '1' to a bit in this register clears the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Disable Register This register is used to disable interrupt sources for the IIC controller. Writing a '1' to a bit in this register sets the corresponding bit in the IIC Interrupt Mask register. Write only. IIC Interrupt Mask Register This register shows the enabled/disabled status of each IIC controller interrupt source. A bit set to 1 will ignore the corresponding interrupt in the status register. A bit set to 0 means the interrupt is enabled. All mask bits are set and all interrupts are disabled after reset. Read only. All four registers have the same bit definitions. They are only defined once for each of the Interrupt Enable Register, Interrupt Disable Register, Interrupt Mask Register, and Interrupt Status Register
#define	XIICPS_IXR_ARB_LOST_MASK 0x00000200U
	Arbitration Lost Interrupt mask. More...

#define	XIICPS_IXR_RX_UNF_MASK 0x00000080U
	FIFO Receive Underflow Interrupt mask. More...

#define	XIICPS_IXR_TX_OVR_MASK 0x00000040U
	Transmit Overflow Interrupt mask. More...

#define	XIICPS_IXR_RX_OVR_MASK 0x00000020U
	Receive Overflow Interrupt mask. More...

#define	XIICPS_IXR_SLV_RDY_MASK 0x00000010U
	Monitored Slave Ready Interrupt mask. More...

#define	XIICPS_IXR_TO_MASK 0x00000008U
	Transfer Time Out Interrupt mask. More...

#define	XIICPS_IXR_NACK_MASK 0x00000004U
	NACK Interrupt mask. More...

#define	XIICPS_IXR_DATA_MASK 0x00000002U
	Data Interrupt mask. More...

#define	XIICPS_IXR_COMP_MASK 0x00000001U
	Transfer Complete Interrupt mask. More...

#define	XIICPS_IXR_DEFAULT_MASK 0x000002FFU
	Default ISR Mask. More...

#define	XIICPS_IXR_ALL_INTR_MASK 0x000002FFU
	All ISR Mask. More...

Macros