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ipipsu
Vitis Drivers API Documentation
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Macros | |
#define | XIPIPSU_HW_H_ |
< prevent circular inclusions More... | |
#define | XIPIPSU_MSG_RAM_BASE 0xFF990000U |
IPI Message RAM base address. More... | |
#define | XIPIPSU_MSG_BUF_SIZE 8U |
Size in Words. More... | |
#define | XIPIPSU_MAX_BUFF_INDEX 7U |
Maximum Buffer Index. More... | |
#define | XIPIPSU_BUFFER_OFFSET_GROUP (8U * 2U * 32U) |
Buffer offset for group. More... | |
#define | XIPIPSU_BUFFER_OFFSET_TARGET (32U * 2U) |
Buffer offset for target. More... | |
#define | XIPIPSU_BUFFER_OFFSET_RESPONSE (32U) |
Buffer offset for response. More... | |
#define | XIPIPSU_MAX_TARGETS XPAR_XIPIPSU_NUM_TARGETS |
Maximum number of targets. More... | |
#define | XIPIPSU_TRIG_OFFSET 0x00U |
Offset for Trigger register. More... | |
#define | XIPIPSU_OBS_OFFSET 0x04U |
Offset for Observation register. More... | |
#define | XIPIPSU_ISR_OFFSET 0x10U |
Offset for ISR register. More... | |
#define | XIPIPSU_IMR_OFFSET 0x14U |
Offset for Interrupt Mask Register. More... | |
#define | XIPIPSU_IER_OFFSET 0x18U |
Offset for Interrupt Enable Register. More... | |
#define | XIPIPSU_IDR_OFFSET 0x1CU |
Offset for Interrupt Disable Register. More... | |
#define | XIPIPSU_ECC_UE_MASK 0x40U |
Uncorrecteble Error mask. More... | |
#define | XIPIPSU_ALL_MASK 0x0F0F0301U |
All valid bit mask. More... | |