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rtcpsu
Vitis Drivers API Documentation
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Macros | |
#define | XRTC_HW_H_ |
< prevent circular inclusions More... | |
#define | XRTC_BASEADDR 0xFFA60000U |
Xrtc Base Address. More... | |
#define | XRtcPsu_ReadReg(RegisterAddr) Xil_In32(RegisterAddr) |
This macro reads the given register. More... | |
#define | XRtcPsu_WriteReg(RegisterAddr, Data) Xil_Out32(RegisterAddr, (u32)(Data)) |
This macro writes the given register. More... | |
Set Timer Register | |
This register contains bits for configuring Current time. | |
#define | XRTC_SET_TIME_WR_OFFSET 0x00000000U |
Register: XrtcSetTimeWr. More... | |
#define | XRTC_SET_TIME_WR_RSTVAL 0x00000000U |
#define | XRTC_SET_TIME_WR_VAL_SHIFT 0U |
#define | XRTC_SET_TIME_WR_VAL_WIDTH 32U |
#define | XRTC_SET_TIME_WR_VAL_MASK 0xffffffffU |
#define | XRTC_SET_TIME_WR_VAL_DEFVAL 0x0U |
#define | XRTC_SET_TIME_RD_OFFSET 0x00000004U |
Register: XrtcSetTimeRd. More... | |
#define | XRTC_SET_TIME_RD_RSTVAL 0x00000000U |
#define | XRTC_SET_TIME_RD_VAL_SHIFT 0U |
#define | XRTC_SET_TIME_RD_VAL_WIDTH 32U |
#define | XRTC_SET_TIME_RD_VAL_MASK 0xffffffffU |
#define | XRTC_SET_TIME_RD_VAL_DEFVAL 0x0U |
Calibration Register | |
This register contains bits for configuring Calibration values. | |
#define | XRTC_CALIB_WR_OFFSET 0x00000008U |
Register: XrtcCalibWr. More... | |
#define | XRTC_CALIB_WR_RSTVAL 0x00000000U |
#define | XRTC_CALIB_WR_FRACTN_EN_SHIFT 20U |
#define | XRTC_CALIB_WR_FRACTN_EN_WIDTH 1U |
#define | XRTC_CALIB_WR_FRACTN_EN_MASK 0x00100000U |
#define | XRTC_CALIB_WR_FRACTN_EN_DEFVAL 0x0U |
#define | XRTC_CALIB_WR_FRACTN_DATA_SHIFT 16U |
#define | XRTC_CALIB_WR_FRACTN_DATA_WIDTH 4U |
#define | XRTC_CALIB_WR_FRACTN_DATA_MASK 0x000f0000U |
#define | XRTC_CALIB_WR_FRACTN_DATA_DEFVAL 0x0U |
#define | XRTC_CALIB_WR_MAX_TCK_SHIFT 0U |
#define | XRTC_CALIB_WR_MAX_TCK_WIDTH 16U |
#define | XRTC_CALIB_WR_MAX_TCK_MASK 0x0000ffffU |
#define | XRTC_CALIB_WR_MAX_TCK_DEFVAL 0x0U |
#define | XRTC_CALIB_RD_OFFSET 0x0000000CU |
Register: XrtcCalibRd. More... | |
#define | XRTC_CALIB_RD_RSTVAL 0x00000000U |
#define | XRTC_CALIB_RD_FRACTN_EN_SHIFT 20U |
#define | XRTC_CALIB_RD_FRACTN_EN_WIDTH 1U |
#define | XRTC_CALIB_RD_FRACTN_EN_MASK 0x00100000U |
#define | XRTC_CALIB_RD_FRACTN_EN_DEFVAL 0x0U |
#define | XRTC_CALIB_RD_FRACTN_DATA_SHIFT 16U |
#define | XRTC_CALIB_RD_FRACTN_DATA_WIDTH 4U |
#define | XRTC_CALIB_RD_FRACTN_DATA_MASK 0x000f0000U |
#define | XRTC_CALIB_RD_FRACTN_DATA_DEFVAL 0x0U |
#define | XRTC_CALIB_RD_MAX_TCK_SHIFT 0U |
#define | XRTC_CALIB_RD_MAX_TCK_WIDTH 16U |
#define | XRTC_CALIB_RD_MAX_TCK_MASK 0x0000ffffU |
#define | XRTC_CALIB_RD_MAX_TCK_DEFVAL 0x0U |
Current time Register | |
This register contains bits for configuring Current time. | |
#define | XRTC_CUR_TIME_OFFSET 0x00000010U |
Register: XrtcCurTime. More... | |
#define | XRTC_CUR_TIME_RSTVAL 0x00000000U |
#define | XRTC_CUR_TIME_VAL_SHIFT 0U |
#define | XRTC_CUR_TIME_VAL_WIDTH 32U |
#define | XRTC_CUR_TIME_VAL_MASK 0xffffffffU |
#define | XRTC_CUR_TIME_VAL_DEFVAL 0x0U |
#define | XRTC_CUR_TCK_OFFSET 0x00000014U |
Register: XrtcCurTck. More... | |
#define | XRTC_CUR_TCK_RSTVAL 0x00000000U |
#define | XRTC_CUR_TCK_VAL_SHIFT 0U |
#define | XRTC_CUR_TCK_VAL_WIDTH 16U |
#define | XRTC_CUR_TCK_VAL_MASK 0x0000ffffU |
#define | XRTC_CUR_TCK_VAL_DEFVAL 0x0U |
Alarm Register | |
This register contains bits for configuring Alarm. | |
#define | XRTC_ALRM_OFFSET 0x00000018U |
Register: XrtcAlrm. More... | |
#define | XRTC_ALRM_RSTVAL 0x00000000U |
#define | XRTC_ALRM_VAL_SHIFT 0U |
#define | XRTC_ALRM_VAL_WIDTH 32U |
#define | XRTC_ALRM_VAL_MASK 0xffffffffU |
#define | XRTC_ALRM_VAL_DEFVAL 0x0U |
Interrupt Status Register | |
This register contains bits for configuring Interrupt. | |
#define | XRTC_INT_STS_OFFSET 0x00000020U |
Register: XrtcIntSts. More... | |
#define | XRTC_INT_STS_RSTVAL 0x00000000U |
#define | XRTC_INT_STS_ALRM_SHIFT 1U |
#define | XRTC_INT_STS_ALRM_WIDTH 1U |
#define | XRTC_INT_STS_ALRM_MASK 0x00000002U |
#define | XRTC_INT_STS_ALRM_DEFVAL 0x0U |
#define | XRTC_INT_STS_SECS_SHIFT 0U |
#define | XRTC_INT_STS_SECS_WIDTH 1U |
#define | XRTC_INT_STS_SECS_MASK 0x00000001U |
#define | XRTC_INT_STS_SECS_DEFVAL 0x0U |
#define | XRTC_INT_MSK_OFFSET 0x00000024U |
Register: XrtcIntMsk. More... | |
#define | XRTC_INT_MSK_RSTVAL 0x00000003U |
#define | XRTC_INT_MSK_ALRM_SHIFT 1U |
#define | XRTC_INT_MSK_ALRM_WIDTH 1U |
#define | XRTC_INT_MSK_ALRM_MASK 0x00000002U |
#define | XRTC_INT_MSK_ALRM_DEFVAL 0x1U |
#define | XRTC_INT_MSK_SECS_SHIFT 0U |
#define | XRTC_INT_MSK_SECS_WIDTH 1U |
#define | XRTC_INT_MSK_SECS_MASK 0x00000001U |
#define | XRTC_INT_MSK_SECS_DEFVAL 0x1U |
#define | XRTC_INT_EN_OFFSET 0x00000028U |
Register: XrtcIntEn. More... | |
#define | XRTC_INT_EN_RSTVAL 0x00000000U |
#define | XRTC_INT_EN_ALRM_SHIFT 1U |
#define | XRTC_INT_EN_ALRM_WIDTH 1U |
#define | XRTC_INT_EN_ALRM_MASK 0x00000002U |
#define | XRTC_INT_EN_ALRM_DEFVAL 0x0U |
#define | XRTC_INT_EN_SECS_SHIFT 0U |
#define | XRTC_INT_EN_SECS_WIDTH 1U |
#define | XRTC_INT_EN_SECS_MASK 0x00000001U |
#define | XRTC_INT_EN_SECS_DEFVAL 0x0U |
#define | XRTC_INT_DIS_OFFSET 0x0000002CU |
Register: XrtcIntDis. More... | |
#define | XRTC_INT_DIS_RSTVAL 0x00000000U |
#define | XRTC_INT_DIS_ALRM_SHIFT 1U |
#define | XRTC_INT_DIS_ALRM_WIDTH 1U |
#define | XRTC_INT_DIS_ALRM_MASK 0x00000002U |
#define | XRTC_INT_DIS_ALRM_DEFVAL 0x0U |
#define | XRTC_INT_DIS_SECS_SHIFT 0U |
#define | XRTC_INT_DIS_SECS_WIDTH 1U |
#define | XRTC_INT_DIS_SECS_MASK 0x00000001U |
#define | XRTC_INT_DIS_SECS_DEFVAL 0x0U |
#define | XRTC_ADD_ERR_OFFSET 0x00000030U |
Register: XrtcAddErr. More... | |
#define | XRTC_ADD_ERR_RSTVAL 0x00000000U |
#define | XRTC_ADD_ERR_STS_SHIFT 0U |
#define | XRTC_ADD_ERR_STS_WIDTH 1U |
#define | XRTC_ADD_ERR_STS_MASK 0x00000001U |
#define | XRTC_ADD_ERR_STS_DEFVAL 0x0U |
#define | XRTC_ADD_ERR_INT_MSK_OFFSET 0x00000034U |
Register: XrtcAddErrIntMsk. More... | |
#define | XRTC_ADD_ERR_INT_MSK_RSTVAL 0x00000001U |
#define | XRTC_ADD_ERR_INT_MSK_SHIFT 0U |
#define | XRTC_ADD_ERR_INT_MSK_WIDTH 1U |
#define | XRTC_ADD_ERR_INT_MSK_MASK 0x00000001U |
#define | XRTC_ADD_ERR_INT_MSK_DEFVAL 0x1U |
#define | XRTC_ADD_ERR_INT_EN_OFFSET 0x00000038U |
Register: XrtcAddErrIntEn. More... | |
#define | XRTC_ADD_ERR_INT_EN_RSTVAL 0x00000000U |
#define | XRTC_ADD_ERR_INT_EN_MSK_SHIFT 0U |
#define | XRTC_ADD_ERR_INT_EN_MSK_WIDTH 1U |
#define | XRTC_ADD_ERR_INT_EN_MSK_MASK 0x00000001U |
#define | XRTC_ADD_ERR_INT_EN_MSK_DEFVAL 0x0U |
#define | XRTC_ADD_ERR_INT_DIS_OFFSET 0x0000003CU |
Register: XrtcAddErrIntDis. More... | |
#define | XRTC_ADD_ERR_INT_DIS_RSTVAL 0x00000000U |
#define | XRTC_ADD_ERR_INT_DIS_MSK_SHIFT 0U |
#define | XRTC_ADD_ERR_INT_DIS_MSK_WIDTH 1U |
#define | XRTC_ADD_ERR_INT_DIS_MSK_MASK 0x00000001U |
#define | XRTC_ADD_ERR_INT_DIS_MSK_DEFVAL 0x0U |
Control Register | |
This register contains bits for control register. | |
#define | XRTC_CTL_OFFSET 0x00000040U |
Register: XrtcCtl. More... | |
#define | XRTC_CTL_RSTVAL 0x01000000U |
#define | XRTC_CTL_BATTERY_EN_SHIFT 31U |
#define | XRTC_CTL_BATTERY_EN_WIDTH 1U |
#define | XRTC_CTL_BATTERY_EN_MASK 0x80000000U |
#define | XRTC_CTL_BATTERY_EN_DEFVAL 0x0U |
#define | XRTC_CTL_OSC_SHIFT 24U |
#define | XRTC_CTL_OSC_WIDTH 4U |
#define | XRTC_CTL_OSC_MASK 0x0f000000U |
#define | XRTC_CTL_OSC_DEFVAL 0x1U |
#define | XRTC_CTL_SLVERR_EN_SHIFT 0U |
#define | XRTC_CTL_SLVERR_EN_WIDTH 1U |
#define | XRTC_CTL_SLVERR_EN_MASK 0x00000001U |
#define | XRTC_CTL_SLVERR_EN_DEFVAL 0x0U |
Safety Check Register | |
This register contains bits for configuring safety check. | |
#define | XRTC_SFTY_CHK_OFFSET 0x00000050U |
Register: XrtcSftyChk. More... | |
#define | XRTC_SFTY_CHK_RSTVAL 0x00000000U |
#define | XRTC_SFTY_CHK_REG_SHIFT 0U |
#define | XRTC_SFTY_CHK_REG_WIDTH 32U |
#define | XRTC_SFTY_CHK_REG_MASK 0xffffffffU |
#define | XRTC_SFTY_CHK_REG_DEFVAL 0x0U |
#define | XRTC_ECO_OFFSET 0x00000060U |
Register: XrtcEco. More... | |
#define | XRTC_ECO_RSTVAL 0x00000000U |
#define | XRTC_ECO_REG_SHIFT 0U |
#define | XRTC_ECO_REG_WIDTH 32U |
#define | XRTC_ECO_REG_MASK 0xffffffffU |
#define | XRTC_ECO_REG_DEFVAL 0x0U |