Macros
#define	XSpi_ReadReg(BaseAddress, RegOffset) XSpi_In32((BaseAddress) + (RegOffset))
	Read from the specified Spi device register. More...

#define	XSpi_WriteReg(BaseAddress, RegOffset, RegisterValue) XSpi_Out32((BaseAddress) + (RegOffset), (RegisterValue))
	Write to the specified Spi device register. More...

#define	XSP_SRR_RESET_MASK 0x0000000A
	SPI Software Reset Register (SRR) mask. More...

Register Map
XSPI register offsets Register offsets for the XSpi device.
#define	XSP_DGIER_OFFSET 0x1C
	Global Intr Enable Reg. More...

#define	XSP_IISR_OFFSET 0x20
	Interrupt status Reg. More...

#define	XSP_IIER_OFFSET 0x28
	Interrupt Enable Reg. More...

#define	XSP_SRR_OFFSET 0x40
	Software Reset register. More...

#define	XSP_CR_OFFSET 0x60
	Control register. More...

#define	XSP_SR_OFFSET 0x64
	Status Register. More...

#define	XSP_DTR_OFFSET 0x68
	Data transmit. More...

#define	XSP_DRR_OFFSET 0x6C
	Data receive. More...

#define	XSP_SSR_OFFSET 0x70
	32-bit slave select More...

#define	XSP_TFO_OFFSET 0x74
	Tx FIFO occupancy. More...

#define	XSP_RFO_OFFSET 0x78
	Rx FIFO occupancy. More...

Global Interrupt Enable Register (GIER) mask(s)
#define	XSP_GINTR_ENABLE_MASK 0x80000000
	Global interrupt enable. More...

SPI Device Interrupt Status/Enable Registers
Interrupt Status Register (IPISR) This register holds the interrupt status flags for the Spi device. Interrupt Enable Register (IPIER) This register is used to enable interrupt sources for the Spi device. Writing a '1' to a bit in this register enables the corresponding Interrupt. Writing a '0' to a bit in this register disables the corresponding Interrupt. ISR/IER registers have the same bit definitions and are only defined once.
#define	XSP_INTR_MODE_FAULT_MASK 0x00000001
	Mode fault error. More...

#define	XSP_INTR_SLAVE_MODE_FAULT_MASK 0x00000002
	Selected as slave while disabled. More...

#define	XSP_INTR_TX_EMPTY_MASK 0x00000004
	DTR/TxFIFO is empty. More...

#define	XSP_INTR_TX_UNDERRUN_MASK 0x00000008
	DTR/TxFIFO underrun. More...

#define	XSP_INTR_RX_FULL_MASK 0x00000010
	DRR/RxFIFO is full. More...

#define	XSP_INTR_RX_OVERRUN_MASK 0x00000020
	DRR/RxFIFO overrun. More...

#define	XSP_INTR_TX_HALF_EMPTY_MASK 0x00000040
	TxFIFO is half empty. More...

#define	XSP_INTR_SLAVE_MODE_MASK 0x00000080
	Slave select mode. More...

#define	XSP_INTR_RX_NOT_EMPTY_MASK 0x00000100
	RxFIFO not empty. More...

#define	XSP_INTR_CPOL_CPHA_ERR_MASK 0x00000200
	The following bits are available only in axi_qspi Interrupt Status and Interrupt Enable registers. More...

#define	XSP_INTR_SLAVE_MODE_ERR_MASK 0x00000400
	Slave mode error. More...

#define	XSP_INTR_MSB_ERR_MASK 0x00000800
	MSB Error. More...

#define	XSP_INTR_LOOP_BACK_ERR_MASK 0x00001000
	Loop back error. More...

#define	XSP_INTR_CMD_ERR_MASK 0x00002000
	'Invalid cmd' error More...

#define	XSP_INTR_ALL
	Mask for all the interrupts in the IP Interrupt Registers. More...

#define	XSP_INTR_DFT_MASK
	The interrupts we want at startup. More...

SPI Control Register (CR) masks
#define	XSP_CR_LOOPBACK_MASK 0x00000001
	Local loopback mode. More...

#define	XSP_CR_ENABLE_MASK 0x00000002
	System enable. More...

#define	XSP_CR_MASTER_MODE_MASK 0x00000004
	Enable master mode. More...

#define	XSP_CR_CLK_POLARITY_MASK 0x00000008
	Clock polarity high or low. More...

#define	XSP_CR_CLK_PHASE_MASK 0x00000010
	Clock phase 0 or 1. More...

#define	XSP_CR_TXFIFO_RESET_MASK 0x00000020
	Reset transmit FIFO. More...

#define	XSP_CR_RXFIFO_RESET_MASK 0x00000040
	Reset receive FIFO. More...

#define	XSP_CR_MANUAL_SS_MASK 0x00000080
	Manual slave select assert. More...

#define	XSP_CR_TRANS_INHIBIT_MASK 0x00000100
	Master transaction inhibit. More...

#define	XSP_CR_RESET_DONE_MASK 0x00000000
	FIFO reset complete. More...

#define	XSP_CR_LSB_MSB_FIRST_MASK 0x00000200
	LSB/MSB first data format select. More...

SPI Control Register (CR) masks for XIP Mode
#define	XSP_CR_XIP_CLK_PHASE_MASK 0x00000001
	Clock phase 0 or 1. More...

#define	XSP_CR_XIP_CLK_POLARITY_MASK 0x00000002
	Clock polarity high or low. More...

Status Register (SR) masks
#define	XSP_SR_RX_EMPTY_MASK 0x00000001
	Receive Reg/FIFO is empty. More...

#define	XSP_SR_RX_FULL_MASK 0x00000002
	Receive Reg/FIFO is full. More...

#define	XSP_SR_TX_EMPTY_MASK 0x00000004
	Transmit Reg/FIFO is empty. More...

#define	XSP_SR_TX_FULL_MASK 0x00000008
	Transmit Reg/FIFO is full. More...

#define	XSP_SR_MODE_FAULT_MASK 0x00000010
	Mode fault error. More...

#define	XSP_SR_SLAVE_MODE_MASK 0x00000020
	Slave mode select. More...

#define	XSP_SR_CPOL_CPHA_ERR_MASK 0x00000040
	CPOL/CPHA error. More...

#define	XSP_SR_SLAVE_MODE_ERR_MASK 0x00000080
	Slave mode error. More...

#define	XSP_SR_MSB_ERR_MASK 0x00000100
	MSB Error. More...

#define	XSP_SR_LOOP_BACK_ERR_MASK 0x00000200
	Loop back error. More...

#define	XSP_SR_CMD_ERR_MASK 0x00000400
	'Invalid cmd' error More...

Status Register (SR) masks for XIP Mode
#define	XSP_SR_XIP_RX_EMPTY_MASK 0x00000001
	Receive Reg/FIFO is empty. More...

#define	XSP_SR_XIP_RX_FULL_MASK 0x00000002
	Receive Reg/FIFO is full. More...

#define	XSP_SR_XIP_MASTER_MODF_MASK 0x00000004
	Receive Reg/FIFO is full. More...

#define	XSP_SR_XIP_CPHPL_ERROR_MASK 0x00000008
	Clock Phase,Clock Polarity Error. More...

#define	XSP_SR_XIP_AXI_ERROR_MASK 0x00000010
	AXI Transaction Error. More...

SPI Transmit FIFO Occupancy (TFO) mask
#define	XSP_TFO_MASK 0x0000001F

SPI Receive FIFO Occupancy (RFO) mask
#define	XSP_RFO_MASK 0x0000001F

Data Width Definitions
#define	XSP_DATAWIDTH_BYTE 8
	Tx/Rx Reg is Byte Wide. More...

#define	XSP_DATAWIDTH_HALF_WORD 16
	Tx/Rx Reg is Half Word (16 bit) Wide. More...

#define	XSP_DATAWIDTH_WORD 32
	Tx/Rx Reg is Word (32 bit) Wide. More...

SPI Modes
The following constants define the modes in which qxi_qspi operates.
#define	XSP_STANDARD_MODE 0

#define	XSP_DUAL_MODE 1

#define	XSP_QUAD_MODE 2

Macros