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usbps
Vitis Drivers API Documentation
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usbps
Vitis Drivers API Documentation
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Macros | |
| #define | XUSBPS_dQH_BASE_ALIGN 2048 |
| Mask for All IRQ Enable masks. More... | |
| #define | XUSBPS_dQH_ALIGN 64 |
| Alignment of a Device Transfer Descriptor structure. More... | |
| #define | XUSBPS_dTD_ALIGN 32 |
| Size of one RX buffer for a OUT Transfer Descriptor. More... | |
| #define | XUSBPS_dTD_BUF_SIZE 4096 |
| Maximum size of one RX/TX buffer. More... | |
| #define | XUSBPS_dTD_BUF_MAX_SIZE 16*1024 |
| Alignment requirement for Transfer Descriptor buffers. More... | |
| #define | XUsbPs_ReadReg(BaseAddress, RegOffset) Xil_In32(BaseAddress + (RegOffset)) |
| This macro reads the given register. More... | |
| #define | XUsbPs_WriteReg(BaseAddress, RegOffset, Data) Xil_Out32(BaseAddress + (RegOffset), (Data)) |
| This macro writes the given register. More... | |
Timer 0 Register offsets | |
| #define | XUSBPS_TIMER0_LD_OFFSET 0x00000080 |
| #define | XUSBPS_TIMER0_CTL_OFFSET 0x00000084 |
Timer Control Register bit mask | |
| #define | XUSBPS_TIMER_RUN_MASK 0x80000000 |
| #define | XUSBPS_TIMER_STOP_MASK 0x80000000 |
| #define | XUSBPS_TIMER_RESET_MASK 0x40000000 |
| #define | XUSBPS_TIMER_REPEAT_MASK 0x01000000 |
| #define | XUSBPS_TIMER_COUNTER_MASK 0x00FFFFFF |
Device Hardware Parameters | |
| #define | XUSBPS_HWDEVICE_OFFSET 0x0000000C |
| #define | XUSBPS_EP_NUM_MASK 0x3E |
| #define | XUSBPS_EP_NUM_SHIFT 1 |
Capability Register offsets | |
| #define | XUSBPS_HCSPARAMS_OFFSET 0x00000104 |
Operational Register offsets. | |
Register comments are tagged with "H:" and "D:" for Host and Device modes, respectively. Tags are only present for registers that have a different meaning DEVICE and HOST modes. Most registers are only valid for either DEVICE or HOST mode. Those registers don't have tags. | |
| #define | XUSBPS_CMD_OFFSET 0x00000140 |
| Configuration. More... | |
| #define | XUSBPS_ISR_OFFSET 0x00000144 |
| Interrupt Status. More... | |
| #define | XUSBPS_IER_OFFSET 0x00000148 |
| Interrupt Enable. More... | |
| #define | XUSBPS_FRAME_OFFSET 0x0000014C |
| USB Frame Index. More... | |
| #define | XUSBPS_LISTBASE_OFFSET 0x00000154 |
| H: Periodic List Base Address. More... | |
| #define | XUSBPS_DEVICEADDR_OFFSET 0x00000154 |
| D: Device Address. More... | |
| #define | XUSBPS_ASYNCLISTADDR_OFFSET 0x00000158 |
| H: Async List Address. More... | |
| #define | XUSBPS_EPLISTADDR_OFFSET 0x00000158 |
| D: Endpoint List Addr. More... | |
| #define | XUSBPS_TTCTRL_OFFSET 0x0000015C |
| TT Control. More... | |
| #define | XUSBPS_BURSTSIZE_OFFSET 0x00000160 |
| Burst Size. More... | |
| #define | XUSBPS_TXFILL_OFFSET 0x00000164 |
| Tx Fill Tuning. More... | |
| #define | XUSBPS_ULPIVIEW_OFFSET 0x00000170 |
| ULPI Viewport. More... | |
| #define | XUSBPS_EPNAKISR_OFFSET 0x00000178 |
| Endpoint NAK IRQ Status. More... | |
| #define | XUSBPS_EPNAKIER_OFFSET 0x0000017C |
| Endpoint NAK IRQ Enable. More... | |
| #define | XUSBPS_PORTSCR1_OFFSET 0x00000184 |
| Port Control/Status 1. More... | |
| #define | XUSBPS_PORTSCRn_OFFSET(n) (XUSBPS_PORTSCR1_OFFSET + (((n)-1) * XUSBPS_REG_SPACING)) |
| #define | XUSBPS_OTGCSR_OFFSET 0x000001A4 |
| OTG Status and Control. More... | |
| #define | XUSBPS_MODE_OFFSET 0x000001A8 |
| USB Mode. More... | |
| #define | XUSBPS_EPSTAT_OFFSET 0x000001AC |
| Endpoint Setup Status. More... | |
| #define | XUSBPS_EPPRIME_OFFSET 0x000001B0 |
| Endpoint Prime. More... | |
| #define | XUSBPS_EPFLUSH_OFFSET 0x000001B4 |
| Endpoint Flush. More... | |
| #define | XUSBPS_EPRDY_OFFSET 0x000001B8 |
| Endpoint Ready. More... | |
| #define | XUSBPS_EPCOMPL_OFFSET 0x000001BC |
| Endpoint Complete. More... | |
| #define | XUSBPS_EPCR0_OFFSET 0x000001C0 |
| Endpoint Control 0. More... | |
| #define | XUSBPS_EPCR1_OFFSET 0x000001C4 |
| Endpoint Control 1. More... | |
| #define | XUSBPS_EPCR2_OFFSET 0x000001C8 |
| Endpoint Control 2. More... | |
| #define | XUSBPS_EPCR3_OFFSET 0x000001CC |
| Endpoint Control 3. More... | |
| #define | XUSBPS_EPCR4_OFFSET 0x000001D0 |
| Endpoint Control 4. More... | |
| #define | XUSBPS_MAX_ENDPOINTS 12 |
| Number of supported Endpoints in this core. More... | |
| #define | XUSBPS_EP_OUT_MASK 0x00000FFF |
| OUR (RX) endpoint mask. More... | |
| #define | XUSBPS_EP_IN_MASK 0x0FFF0000 |
| IN (TX) endpoint mask. More... | |
| #define | XUSBPS_EP_ALL_MASK 0x0FFF0FFF |
| Mask used for endpoint control registers. More... | |
| #define | XUSBPS_EPCRn_OFFSET(n) (XUSBPS_EPCR0_OFFSET + ((n) * XUSBPS_REG_SPACING)) |
| #define | XUSBPS_EPFLUSH_RX_SHIFT 0 |
| #define | XUSBPS_EPFLUSH_TX_SHIFT 16 |
Endpoint Control Register (EPCR) bit positions. | |
| #define | XUSBPS_EPCR_TXT_TYPE_SHIFT 18 /* < Endpoint Type - TX bit shift*/ |
| #define | XUSBPS_EPCR_TXT_TYPE_MASK 0x000C0000 /* < Endpoint Type - TX read only*/ |
| #define | XUSBPS_EPCR_TXT_CONTROL_MASK 0x00000000 |
| Control Endpoint - TX. More... | |
| #define | XUSBPS_EPCR_TXT_ISO_MASK 0x00040000 |
| Isochronous. More... | |
| #define | XUSBPS_EPCR_TXT_BULK_MASK 0x00080000 |
| Bulk Endpoint - TX. More... | |
| #define | XUSBPS_EPCR_TXT_INTR_MASK 0x000C0000 |
| Interrupt Endpoint. More... | |
| #define | XUSBPS_EPCR_TXS_MASK 0x00010000 |
| Stall TX endpoint. More... | |
| #define | XUSBPS_EPCR_TXE_MASK 0x00800000 |
| Transmit enable - TX. More... | |
| #define | XUSBPS_EPCR_TXR_MASK 0x00400000 |
| Data Toggle Reset Bit. More... | |
| #define | XUSBPS_EPCR_RXT_TYPE_SHIFT 2 /* < Endpoint Type - RX bit shift*/ |
| #define | XUSBPS_EPCR_RXT_TYPE_MASK 0x0000000C |
| Endpoint Type - RX read only. More... | |
| #define | XUSBPS_EPCR_RXT_CONTROL_MASK 0x00000000 |
| Control Endpoint - RX. More... | |
| #define | XUSBPS_EPCR_RXT_ISO_MASK 0x00000004 |
| Isochronous Endpoint. More... | |
| #define | XUSBPS_EPCR_RXT_BULK_MASK 0x00000008 |
| Bulk Endpoint - RX. More... | |
| #define | XUSBPS_EPCR_RXT_INTR_MASK 0x0000000C |
| Interrupt Endpoint. More... | |
| #define | XUSBPS_EPCR_RXS_MASK 0x00000001 |
| Stall RX endpoint. More... | |
| #define | XUSBPS_EPCR_RXE_MASK 0x00000080 |
| Transmit enable. More... | |
| #define | XUSBPS_EPCR_RXR_MASK 0x00000040 |
| Data Toggle Reset Bit. More... | |
USB Command Register (CR) bit positions. | |
| #define | XUSBPS_CMD_RS_MASK 0x00000001 |
| Run/Stop. More... | |
| #define | XUSBPS_CMD_RST_MASK 0x00000002 |
| Controller RESET. More... | |
| #define | XUSBPS_CMD_FS01_MASK 0x0000000C |
| Frame List Size bit 0,1. More... | |
| #define | XUSBPS_CMD_PSE_MASK 0x00000010 |
| Periodic Sched Enable. More... | |
| #define | XUSBPS_CMD_ASE_MASK 0x00000020 |
| Async Sched Enable. More... | |
| #define | XUSBPS_CMD_IAA_MASK 0x00000040 |
| IRQ Async Advance Doorbell. More... | |
| #define | XUSBPS_CMD_ASP_MASK 0x00000300 |
| Async Sched Park Mode Cnt. More... | |
| #define | XUSBPS_CMD_ASPE_MASK 0x00000800 |
| Async Sched Park Mode Enbl. More... | |
| #define | XUSBPS_CMD_SUTW_MASK 0x00002000 |
| Setup TripWire. More... | |
| #define | XUSBPS_CMD_ATDTW_MASK 0x00004000 |
| Add dTD TripWire. More... | |
| #define | XUSBPS_CMD_FS2_MASK 0x00008000 |
| Frame List Size bit 2. More... | |
| #define | XUSBPS_CMD_ITC_MASK 0x00FF0000 |
| IRQ Threshold Control. More... | |
Interrupt Threshold | |
These definitions are used by software to set the maximum rate at which the USB controller will generate interrupt requests. The interrupt interval is given in number of micro-frames. USB defines a full-speed 1 ms frame time indicated by a Start Of Frame (SOF) packet each and every 1ms. USB also defines a high-speed micro-frame with a 125us frame time. For each micro-frame a SOF (Start Of Frame) packet is generated. Data is sent in between the SOF packets. The interrupt threshold defines how many micro-frames the controller waits before issuing an interrupt after data has been received. For a threshold of 0 the controller will issue an interrupt immediately after the last byte of the data has been received. For a threshold n>0 the controller will wait for n micro-frames before issuing an interrupt. Therefore, a setting of 8 micro-frames (default) means that the controller will issue at most 1 interrupt per millisecond. | |
| #define | XUSBPS_CMD_ITHRESHOLD_0 0x00 |
| Immediate interrupt. More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_1 0x01 |
| 1 micro-frame More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_2 0x02 |
| 2 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_4 0x04 |
| 4 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_8 0x08 |
| 8 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_16 0x10 |
| 16 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_32 0x20 |
| 32 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_64 0x40 |
| 64 micro-frames More... | |
| #define | XUSBPS_CMD_ITHRESHOLD_MAX XUSBPS_CMD_ITHRESHOLD_64 |
| #define | XUSBPS_CMD_ITHRESHOLD_DEFAULT XUSBPS_CMD_ITHRESHOLD_8 |
USB Interrupt Status Register (ISR) / Interrupt Enable Register (IER) | |
bit positions. | |
| #define | XUSBPS_IXR_UI_MASK 0x00000001 |
| USB Transaction Complete. More... | |
| #define | XUSBPS_IXR_UE_MASK 0x00000002 |
| Transaction Error. More... | |
| #define | XUSBPS_IXR_PC_MASK 0x00000004 |
| Port Change Detect. More... | |
| #define | XUSBPS_IXR_FRE_MASK 0x00000008 |
| Frame List Rollover. More... | |
| #define | XUSBPS_IXR_AA_MASK 0x00000020 |
| Async Advance. More... | |
| #define | XUSBPS_IXR_UR_MASK 0x00000040 |
| RESET Received. More... | |
| #define | XUSBPS_IXR_SR_MASK 0x00000080 |
| Start of Frame. More... | |
| #define | XUSBPS_IXR_SLE_MASK 0x00000100 |
| Device Controller Suspend. More... | |
| #define | XUSBPS_IXR_ULPI_MASK 0x00000400 |
| ULPI IRQ. More... | |
| #define | XUSBPS_IXR_HCH_MASK 0x00001000 |
| Host Controller Halted Read Only. More... | |
| #define | XUSBPS_IXR_RCL_MASK 0x00002000 |
| USB Reclamation Read Only. More... | |
| #define | XUSBPS_IXR_PS_MASK 0x00004000 |
| Periodic Sched Status Read Only. More... | |
| #define | XUSBPS_IXR_AS_MASK 0x00008000 |
| Async Sched Status Read only. More... | |
| #define | XUSBPS_IXR_NAK_MASK 0x00010000 |
| NAK IRQ. More... | |
| #define | XUSBPS_IXR_UA_MASK 0x00040000 |
| USB Host Async IRQ. More... | |
| #define | XUSBPS_IXR_UP_MASK 0x00080000 |
| USB Host Periodic IRQ. More... | |
| #define | XUSBPS_IXR_TI0_MASK 0x01000000 |
| Timer 0 Interrupt. More... | |
| #define | XUSBPS_IXR_TI1_MASK 0x02000000 |
| Timer 1 Interrupt. More... | |
| #define | XUSBPS_IXR_ALL |
| Mask for ALL IRQ types. More... | |
USB Mode Register (MODE) bit positions. | |
| #define | XUSBPS_MODE_CM_MASK 0x00000003 |
| Controller Mode Select. More... | |
| #define | XUSBPS_MODE_CM_IDLE_MASK 0x00000000 |
| #define | XUSBPS_MODE_CM_DEVICE_MASK 0x00000002 |
| #define | XUSBPS_MODE_CM_HOST_MASK 0x00000003 |
| #define | XUSBPS_MODE_ES_MASK 0x00000004 |
| USB Endian Select. More... | |
| #define | XUSBPS_MODE_SLOM_MASK 0x00000008 |
| USB Setup Lockout Mode Disable. More... | |
| #define | XUSBPS_MODE_SDIS_MASK 0x00000010 |
| #define | XUSBPS_MODE_VALID_MASK 0x0000001F |
USB Device Address Register (DEVICEADDR) bit positions. | |
| #define | XUSBPS_DEVICEADDR_DEVICEAADV_MASK 0x01000000 |
| Device Addr Auto Advance. More... | |
| #define | XUSBPS_DEVICEADDR_ADDR_MASK 0xFE000000 |
| Device Address. More... | |
| #define | XUSBPS_DEVICEADDR_ADDR_SHIFT 25 |
| Address shift. More... | |
| #define | XUSBPS_DEVICEADDR_MAX 127 |
| Biggest allowed address. More... | |
USB TT Control Register (TTCTRL) bit positions. | |
| #define | XUSBPS_TTCTRL_HUBADDR_MASK 0x7F000000 |
| TT Hub Address. More... | |
USB Burst Size Register (BURSTSIZE) bit posisions. | |
| #define | XUSBPS_BURSTSIZE_RX_MASK 0x000000FF |
| RX Burst Length. More... | |
| #define | XUSBPS_BURSTSIZE_TX_MASK 0x0000FF00 |
| TX Burst Length. More... | |
USB Tx Fill Tuning Register (TXFILL) bit positions. | |
| #define | XUSBPS_TXFILL_OVERHEAD_MASK 0x000000FF |
| Scheduler Overhead. More... | |
| #define | XUSBPS_TXFILL_HEALTH_MASK 0x00001F00 |
| Scheduler Health Cntr. More... | |
| #define | XUSBPS_TXFILL_BURST_MASK 0x003F0000 |
| FIFO Burst Threshold. More... | |
USB ULPI Viewport Register (ULPIVIEW) bit positions. | |
| #define | XUSBPS_ULPIVIEW_DATWR_MASK 0x000000FF |
| ULPI Data Write. More... | |
| #define | XUSBPS_ULPIVIEW_DATRD_MASK 0x0000FF00 |
| ULPI Data Read. More... | |
| #define | XUSBPS_ULPIVIEW_ADDR_MASK 0x00FF0000 |
| ULPI Data Address. More... | |
| #define | XUSBPS_ULPIVIEW_PORT_MASK 0x07000000 |
| ULPI Port Number. More... | |
| #define | XUSBPS_ULPIVIEW_SS_MASK 0x08000000 |
| ULPI Synchronous State. More... | |
| #define | XUSBPS_ULPIVIEW_RW_MASK 0x20000000 |
| ULPI Read/Write Control. More... | |
| #define | XUSBPS_ULPIVIEW_RUN_MASK 0x40000000 |
| ULPI Run. More... | |
| #define | XUSBPS_ULPIVIEW_WU_MASK 0x80000000 |
| ULPI Wakeup. More... | |
Port Status Control Register bit positions. | |
| #define | XUSBPS_PORTSCR_CCS_MASK 0x00000001 |
| Current Connect Status. More... | |
| #define | XUSBPS_PORTSCR_CSC_MASK 0x00000002 |
| Connect Status Change. More... | |
| #define | XUSBPS_PORTSCR_PE_MASK 0x00000004 |
| Port Enable/Disable. More... | |
| #define | XUSBPS_PORTSCR_PEC_MASK 0x00000008 |
| Port Enable/Disable Change. More... | |
| #define | XUSBPS_PORTSCR_OCA_MASK 0x00000010 |
| Over-current Active. More... | |
| #define | XUSBPS_PORTSCR_OCC_MASK 0x00000020 |
| Over-current Change. More... | |
| #define | XUSBPS_PORTSCR_FPR_MASK 0x00000040 |
| Force Port Resume. More... | |
| #define | XUSBPS_PORTSCR_SUSP_MASK 0x00000080 |
| Suspend. More... | |
| #define | XUSBPS_PORTSCR_PR_MASK 0x00000100 |
| Port Reset. More... | |
| #define | XUSBPS_PORTSCR_HSP_MASK 0x00000200 |
| High Speed Port. More... | |
| #define | XUSBPS_PORTSCR_LS_MASK 0x00000C00 |
| Line Status. More... | |
| #define | XUSBPS_PORTSCR_PP_MASK 0x00001000 |
| Port Power. More... | |
| #define | XUSBPS_PORTSCR_PO_MASK 0x00002000 |
| Port Owner. More... | |
| #define | XUSBPS_PORTSCR_PIC_MASK 0x0000C000 |
| Port Indicator Control. More... | |
| #define | XUSBPS_PORTSCR_PTC_MASK 0x000F0000 |
| Port Test Control. More... | |
| #define | XUSBPS_PORTSCR_WKCN_MASK 0x00100000 |
| Wake on Connect Enable. More... | |
| #define | XUSBPS_PORTSCR_WKDS_MASK 0x00200000 |
| Wake on Disconnect Enable. More... | |
| #define | XUSBPS_PORTSCR_WKOC_MASK 0x00400000 |
| Wake on Over-current Enable. More... | |
| #define | XUSBPS_PORTSCR_PHCD_MASK 0x00800000 |
| PHY Low Power Suspend - Clock Disable. More... | |
| #define | XUSBPS_PORTSCR_PFSC_MASK 0x01000000 |
| Port Force Full Speed Connect. More... | |
| #define | XUSBPS_PORTSCR_PSPD_MASK 0x0C000000 |
| Port Speed. More... | |
On-The-Go Status Control Register (OTGCSR) bit positions. | |
| #define | XUSBPS_OTGSC_VD_MASK 0x00000001 |
| VBus Discharge Bit. More... | |
| #define | XUSBPS_OTGSC_VC_MASK 0x00000002 |
| VBus Charge Bit. More... | |
| #define | XUSBPS_OTGSC_HAAR_MASK 0x00000004 |
| HW Assist Auto Reset Enable Bit. More... | |
| #define | XUSBPS_OTGSC_OT_MASK 0x00000008 |
| OTG Termination Bit. More... | |
| #define | XUSBPS_OTGSC_DP_MASK 0x00000010 |
| Data Pulsing Pull-up Enable Bit. More... | |
| #define | XUSBPS_OTGSC_IDPU_MASK 0x00000020 |
| ID Pull-up Enable Bit. More... | |
| #define | XUSBPS_OTGSC_HADP_MASK 0x00000040 |
| HW Assist Data Pulse Enable Bit. More... | |
| #define | XUSBPS_OTGSC_HABA_MASK 0x00000080 |
| USB Hardware Assist B Disconnect to A Connect Enable Bit. More... | |
| #define | XUSBPS_OTGSC_ID_MASK 0x00000100 |
| ID Status Flag. More... | |
| #define | XUSBPS_OTGSC_AVV_MASK 0x00000200 |
| USB A VBus Valid Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_ASV_MASK 0x00000400 |
| USB A Session Valid Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_BSV_MASK 0x00000800 |
| USB B Session Valid Status Flag. More... | |
| #define | XUSBPS_OTGSC_BSE_MASK 0x00001000 |
| USB B Session End Status Flag. More... | |
| #define | XUSBPS_OTGSC_1MST_MASK 0x00002000 |
| USB 1 Millisecond Timer Status Flag. More... | |
| #define | XUSBPS_OTGSC_DPS_MASK 0x00004000 |
| Data Pulse Status Flag. More... | |
| #define | XUSBPS_OTGSC_IDIS_MASK 0x00010000 |
| USB ID Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_AVVIS_MASK 0x00020000 |
| USB A VBus Valid Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_ASVIS_MASK 0x00040000 |
| USB A Session Valid Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_BSVIS_MASK 0x00080000 |
| USB B Session Valid Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_BSEIS_MASK 0x00100000 |
| USB B Session End Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_1MSS_MASK 0x00200000 |
| 1 Millisecond Timer Interrupt Status Flag More... | |
| #define | XUSBPS_OTGSC_DPIS_MASK 0x00400000 |
| Data Pulse Interrupt Status Flag. More... | |
| #define | XUSBPS_OTGSC_IDIE_MASK 0x01000000 |
| ID Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTGSC_AVVIE_MASK 0x02000000 |
| USB A VBus Valid Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTGSC_ASVIE_MASK 0x04000000 |
| USB A Session Valid Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTGSC_BSVIE_MASK 0x08000000 |
| USB B Session Valid Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTGSC_BSEE_MASK 0x10000000 |
| USB B Session End Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTGSC_1MSE_MASK 0x20000000 |
| 1 Millisecond Timer Interrupt Enable Bit More... | |
| #define | XUSBPS_OTGSC_DPIE_MASK 0x40000000 |
| Data Pulse Interrupt Enable Bit. More... | |
| #define | XUSBPS_OTG_ISB_ALL |
| #define | XUSBPS_OTG_IEB_ALL |
| Mask for All IRQ status masks. More... | |
Functions | |
| void | XUsbPs_ResetHw (u32 BaseAddress) |
| This function perform the reset sequence to the given usbps interface by configuring the appropriate control bits in the usbps specific registers. More... | |