MLIR-AIE 1.4.6.dev
AIEResourceStages.cpp
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1//===- AIEResourceStages.cpp ------------------------------------*- C++ -*-===//
2//
3// Copyright (C) 2026 Advanced Micro Devices, Inc.
4// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
5//
6//===----------------------------------------------------------------------===//
7
10
11#include "mlir/Conversion/AffineToStandard/AffineToStandard.h"
12#include "mlir/Pass/PassManager.h"
13#include "mlir/Pass/PassRegistry.h"
14
15using namespace mlir;
16using namespace xilinx;
17using namespace xilinx::AIE;
18
19void AIEX::addPlacementStage(OpPassManager &pm,
20 const AIEPlaceTilesOptions &options) {
21 pm.nest<DeviceOp>().addPass(createAIEPlaceTilesPass(options));
22}
23
24void AIEX::addTraceStage(OpPassManager &pm) {
25 OpPassManager &dpm = pm.nest<DeviceOp>();
26 dpm.addPass(createAIEInsertTraceFlowsPass());
27 dpm.addPass(createAIETraceToConfigPass());
30 // Module-level: it rewrites callers and callees together.
32}
33
34void AIEX::addLoweringStage(OpPassManager &pm, bool dynamicObjFifos,
35 bool packetSwObjFifos, bool ctrlPktOverlay,
36 bool loadPdiToCtrlPkt, bool skipObjectFifoVerify,
37 llvm::ArrayRef<int> coverColumns,
38 bool adaptiveOverlay, bool checkQueueSpace) {
39 pm.addPass(createLowerAffinePass());
41 // Before lock IDs and buffer addresses, which its new locks and buffers need.
43
44 pm.nest<DeviceOp>().addPass(createAIEObjectFifoSplitPass());
45 if (!skipObjectFifoVerify)
46 pm.nest<DeviceOp>().addPass(createAIEObjectFifoVerifyPass());
47 AIEGenerateColumnControlOverlayOptions overlay;
48 overlay.configuration = ctrlPktOverlay || loadPdiToCtrlPkt;
49 overlay.adaptive = adaptiveOverlay;
50 overlay.coverColumns = llvm::to_vector(coverColumns);
52 pm.addPass(createAIEImportOverlayPass());
54 OpPassManager &dpm = pm.nest<DeviceOp>();
55 dpm.addPass(createAIEAssignPacketIdsPass(packetSwObjFifos, ctrlPktOverlay));
57 AIEObjectFifoInsertCoreQueuePushesOptions pushOptions;
58 pushOptions.checkQueueSpace = checkQueueSpace;
59 dpm.addPass(createAIEObjectFifoInsertCoreQueuePushesPass(pushOptions));
63 AIEObjectFifoUnrollOptions unroll;
64 unroll.clDefaultDynamic = dynamicObjFifos;
65 dpm.addPass(createAIEObjectFifoUnrollPass(unroll));
67 dpm.addPass(createAIEAssignLockIDsPass());
71 dpm.addPass(createAIELowerCascadeFlowsPass());
72 dpm.addPass(createAIEBroadcastPacketPass());
73 dpm.addPass(createAIELowerMulticastPass());
74 pm.nest<DeviceOp>().addPass(createAIEAssignTileCtrlIDsPass());
75
76 // A buffer's name becomes a symbol in its core's object.
77 pm.nest<DeviceOp>().addPass(createAIEPrepareBuffersPass());
78}
79
80void AIEX::addBufferAddressStage(OpPassManager &pm, int64_t placementBudget) {
81 AIEAssignBufferAddressesOptions options;
82 options.clPlacementBudget = placementBudget;
83 pm.nest<DeviceOp>().addPass(createAIEAssignBufferAddressesPass(options));
84}
85
86void AIEX::addRoutingStage(OpPassManager &pm, bool allowDeadlockProne) {
87 pm.nest<DeviceOp>().addPass(createAIESplitFlowViasPass());
88 OpPassManager &dpm = pm.nest<DeviceOp>();
89 AIERoutePathfinderFlowsOptions options;
90 options.clAllowDeadlockProne = allowDeadlockProne;
91 dpm.addPass(createAIEPathfinderPass(options));
92}
93
95 PassPipelineRegistration<AIEResourceStagesOptions>(
96 "aie-resource-stages",
97 "aiecc's placement, trace, lowering, buffer address and routing stages",
98 [](OpPassManager &pm, const AIEResourceStagesOptions &options) {
99 AIEPlaceTilesOptions place;
100 place.clPlacerType = options.placer;
101 place.clCoresPerCol = options.coresPerCol;
102 place.clSASeed = options.saSeed;
103 place.clSAEffort = options.saEffort;
104 addPlacementStage(pm, place);
105 addTraceStage(pm);
107 options.ctrlPktOverlay || options.loadPdiToCtrlPkt,
108 options.loadPdiToCtrlPkt, options.skipObjectFifoVerify,
109 {}, options.adaptiveOverlay);
112 });
113}
void addLoweringStage(mlir::OpPassManager &pm, bool dynamicObjFifos, bool packetSwObjFifos, bool ctrlPktOverlay, bool loadPdiToCtrlPkt, bool skipObjectFifoVerify, llvm::ArrayRef< int > coverColumns={}, bool adaptiveOverlay=true, bool checkQueueSpace=true)
Affine lowering through aie-prepare-buffers.
std::unique_ptr< mlir::OperationPass< AIE::DeviceOp > > createAIEReserveRuntimeBDIDsPass()
void addBufferAddressStage(mlir::OpPassManager &pm, int64_t placementBudget)
void addRoutingStage(mlir::OpPassManager &pm, bool allowDeadlockProne)
void addPlacementStage(mlir::OpPassManager &pm, const AIE::AIEPlaceTilesOptions &options)
aiecc's stages that give a design its tiles, locks, BD IDs, buffers and routes, in its order.
std::unique_ptr< mlir::OperationPass< AIE::DeviceOp > > createAIEXInlineTraceConfigPass()
void registerAIEResourceStagesPipeline()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIELowerScratchpadParametersPass()
std::unique_ptr< mlir::OperationPass< AIE::DeviceOp > > createAIELowerMulticastPass()
std::unique_ptr< mlir::OperationPass< AIE::DeviceOp > > createAIEBroadcastPacketPass()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIEFuseTraceBuffersPass()
void addTraceStage(mlir::OpPassManager &pm)
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEInsertTraceFlowsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIETraceRegPackWritesPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEPrepareBuffersPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoLowerCoresPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIELowerCoreIssuedConfigurationPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoInsertCoreQueuePushesPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignTileCtrlIDsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIELowerCascadeFlowsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoAllocatePass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIENormalizeDmaBdDimsPass()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIEGenerateColumnControlOverlayPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignLockIDsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEPlaceTilesPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoUnrollPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignPacketIdsPass()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIEAnnotateShimSharingPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIESplitFlowViasPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoErasePoolsPass()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIECanonicalizeDevicePass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignBufferAddressesPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoVerifyPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIETraceToConfigPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEAssignBufferDescriptorIDsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoLowerDMAsPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEPathfinderPass()
std::unique_ptr< mlir::OperationPass< DeviceOp > > createAIEObjectFifoSplitPass()
std::unique_ptr< mlir::OperationPass< mlir::ModuleOp > > createAIEImportOverlayPass()
Options of aie-resource-stages, named and defaulted as aiecc's flags.
Definition AIEXPasses.h:120
Option< AIE::PlacerType > placer
Definition AIEXPasses.h:121