MLIR-AIE 1.4.5.dev
ConnectivityAnalysis Member List

This is the complete list of members for ConnectivityAnalysis, including all inherited members.

ConnectivityAnalysis(DeviceOp &d)ConnectivityAnalysisinline
decodePort(int e)ConnectivityAnalysisinlinestatic
drivesPort(Operation *op, Port port) constConnectivityAnalysisinline
enableSectionSplitting()ConnectivityAnalysisinline
getCircuitFanoutSeeds()ConnectivityAnalysisinline
getConnectedTiles(TileOp tileOp, Port port, bool keepPartialFlows, MaskValue claim={0, 0}) constConnectivityAnalysisinline
getConnectedTilesFromCircuitFanout(const CircuitFanoutSeed &seed, bool keepPartialFlows) constConnectivityAnalysisinline
getConnectedTilesFromEgress(Operation *switchOp, Port egressPort, bool keepPartialFlows, MaskValue claim={0, 0}) constConnectivityAnalysisinline
getConnectedTilesFromInput(Operation *switchOp, Port inputPort, bool keepPartialFlows, MaskValue claim={0, 0}) constConnectivityAnalysisinline
getFanoutEgressSeeds()ConnectivityAnalysisinline
getPacketMergeEgresses()ConnectivityAnalysisinline
getPacketMergeOps() constConnectivityAnalysisinline
traverse(std::vector< PacketConnection > worklist, bool keepPartialFlows) constConnectivityAnalysisinline
upstreamOf(Operation *op, Port port) constConnectivityAnalysisinline