General Debug ChecklistΒΆ
- Confirm the clocking architecture is correct
- Confirm the reset connection is correct
- Check the status of Phy Status Control Register
- If the issue is related to incoming or outgoing packets from the user logic, check the following interface signals in Vivado ILA
- If there is an issue with bridge register reads or write, check the following interface
- For interrupt related issues, check the following signals and register:
- For Root Port related issues, check:
Note
Please refer to the latest version of PG194 for new updates and more details on referenced signals and registers.