General Debug Checklist

• Confirm the clocking architecture is correct

  • Clocking Diagram (UltraScale+ Devices)

• Confirm the reset connection is correct

  • Endpoint:

    • Endpoint System Reset Connection (UltraScale+ Devices)

  • Rootport:

    • Root Port System Reset Connection (UltraScale+ Devices)

• Check the status of Phy Status Control Register

  • PHY Status_Control Register

• If the issue is related to incoming or outgoing packets from the user logic, check the following interface signals in Vivado ILA

  • AXI Slave Interface Signals

  • AXI Master Interface Signals

• If there is an issue with bridge register reads or write, check the following interface

  • AXI4-Lite Control Interface Signals

• For interrupt related issues, check the following signals and register:

  • AXI Bridge for PCIe Gen3 MSI Signals

  • AXI Bridge for PCIe Gen3 MSI-X Signals

  • DMA_Bridge Subsystem for PCIe in Bridge Mode Interrupt Signals

• For Root Port related issues, check:

  • Root Port Status_Control Register

  • Root Port Error FIFO Read Register

  • Interrupt Decode Register

Note

Please refer to the latest version of PG194 for new updates and more details on referenced signals and registers.