Supporting Documentation

For additional reference and relevant information, users can consult the following links:

• Zynq UltraScale+ MPSoC (PS-PCIe/PL-PCIE XDMA Bridge) /Versal Adaptive SoC (CPM/PL-PCIE QDMA Bridge) - Drivers Release Notes - Article 70702

• Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express - Release Notes and Known Issues - Article 75396

• Xilinx GitHub Repository - Versal CPM Bridge RP Design

• Xilinx Wiki - PCIe Root Port Drivers Landing Page

• Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide - Root Port Documentation

• Xilinx Wiki - Versal Adaptive SoC CPM Root Port Linux Driver