Global Error Registers¶
QDMA_GLBL_ERR_STAT
QDMA_GLBL_TRQ_ERR_STS
Ram Single Bit Error¶
QDMA_RAM_SBE_STS_A
Ram Double Bit Error¶
QDMA_RAM_DBE_STS_A
Descriptor Engine Error¶
QDMA_GLBL_DSC_ERR_STS
QDMA_GLBL_DSC_ERR_LOG0
QDMA_GLBL_DSC_ERR_LOG1
QDMA_GLBL_DSC_DBG_DAT0
QDMA_GLBL_DSC_DBG_DAT1
QDMA_GLBL_DSC_DBG_CTL
QDMA_GLBL_DSC_ERR_LOG2
Target Access Error¶
QDMA_GLBL_TRQ_ERR_STS
QDMA_GLBL_TRQ_ERR_LOG
MM H2C Engine Error¶
QDMA_QDMA_H2C_MM_Status
QDMA_H2C_MM_Error_Code
QDMA_H2C_MM_Error_Info
QDMA_H2C_MM_Debug
MM C2H Engine Error¶
QDMA_C2H_MM_Status
C2H_Channel_Completed_Descriptor_Count
QDMA_C2H_MM_Error_Code
QDMA_C2H_MM_Error_Info
QDMA_C2H_MM_Debug
ST C2H Engine Error¶
QDMA_C2H_ERR_STAT
QDMA_C2H_FATAL_ERR_STAT
QDMA_C2H_FIRST_ERR_QID
QDMA_C2H_STAT_S_AXIS_C2H_ACCEPTED
QDMA_C2H_STAT_S_AXIS_WRB_ACCEPTED
QDMA_C2H_STAT_DESC_RSP_PKT_ACCEPTED
QDMA_C2H_STAT_DEBUG_DMA_ENG_0
QDMA_C2H_STAT_DEBUG_DMA_ENG_1
QDMA_C2H_STAT_DEBUG_DMA_ENG_2
QDMA_C2H_STAT_DEBUG_DMA_ENG_3
QDMA_C2H_STAT_DESC_RSP_DROP_ACCEPTED
QDMA_C2H_STAT_DESC_RSP_ERR_ACCEPTED
ST H2C Engine Error¶
QDMA_H2C_ERR_STAT
QDMA_H2C_DBG_REG0
QDMA_H2C_DBG_REG1
QDMA_H2C_DBG_REG2
QDMA_H2C_DBG_REG3
QDMA_H2C_DBG_REG4
In-Direct Interrupt¶
QDMA_C2H_INTR_H2C_REQ
QDMA_C2H_INTR_H2C_REQ
QDMA_C2H_INTR_C2H_MM_REQ
QDMA_C2H_INTR_ERR_INT_REQ
QDMA_C2H_INTR_C2H_ST_REQ
QDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_ACK
QDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_FAIL
QDMA_C2H_INTR_H2C_ERR_C2H_MM_MSIX_NO_MSIX
QDMA_C2H_INTR_H2C_ERR_C2H_MM_CTXT_INVAL
QDMA_C2H_INTR_C2H_ST_MSIX_ACK
QDMA_C2H_INTR_C2H_ST_MSIX_FAIL
QDMA_C2H_INTR_C2H_ST_NO_MSIX
QDMA_C2H_INTR_C2H_ST_CTXT_INVAL