Ethernet TRD

The Ethernet platform demonstrates the functionality of the Multi Rate Media Access Control IP (MRMAC) used for transfer of Ethernet and Precision Time Protocol (PTP) packets from the Network Interface Card (NIC) on a host machine to the board and vice versa. The MRMAC IP is present in the programmable logic of the FPGA design. The Programmable Logic also has PTP Packet Processors in both Transmit and Receive Direction.

Features

• 4x10G/4x25G configuration
• Run-time switchability between 10G and 25G
• 1-step and 2-step Precision Time Protocol (PTP)
• PL based PTP Packet processors for 1-step and 2-Step PTP operation

Quick Start

• Design Overview
• Setting up the Board and Application Deployment

Tutorials

• Using Vivado to Build the Hardware Design
• Building Petalinux

Architecture Documents

• Software Architecture of the Platform
• Hardware Architecture of the Platform
• Hardware Acchitecture of the PTP Packet Processor

Other

• Known Issues

Xilinx Support

GitHub issues will be used for tracking requests and bugs. For questions go to [forums.xilinx.com](http://forums.xilinx.com/).

License

Licensed under the Apache License, Version 2.0 (the “License”); you may not use this file except in compliance with the License.

You may obtain a copy of the License at [http://www.apache.org/licenses/LICENSE-2.0](http://www.apache.org/licenses/LICENSE-2.0)

Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an “AS IS” BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.