This page cover other software and frameworks that may be useful to generate or to deploy your designs. If you would like to contribute your framework to this page, please follow the contribution guidelines
PYNQ is an open-source project from AMD that makes it easier to use Adaptive Computing platforms. Using the Python language and libraries, designers can exploit the benefits of programmable logic and to build more capable and exciting electronic systems. PYNQ can be used with Zynq, Zynq UltraScale+, Zynq RFSoC, Alveo accelerator cards and AWS-F1 to create high performance applications. PYNQ is available by default on the ETH HACC. Find out more in the pynq.io page
Fast, Scalable Quantized Neural Network Inference on FPGAs. Explore deep neural network inference on FPGAs. It specifically targets quantized neural networks, with emphasis on generating dataflow-style architectures customized for each network. Find out more in the finn repository
ACCL: Alveo Collective Communication Library. ACCL is a Vitis kernel and associated XRT drivers which together provide MPI-like collectives for Xilinx FPGAs. ACCL is designed to enable compute kernels resident in FPGA fabric to communicate directly under host supervision but without requiring data movement between the FPGA and host. Find out more in the ACCL repository
This framework is ideal to scale out your application without CPU intervention, full TCP/IP support in the Alveo card. ETH Zurich provides example designs with TCP/IP support at 100 Gbps in Vitis. Find out more in the Vitis 100Gbps TCP/IP repository
The OpenNIC project provides an FPGA-based NIC platform for the open source community. It consists of multiple components: a NIC shell, a Linux kernel driver, and a DPDK driver. The NIC shell contains the RTL sources and design files for targetting several of the AMD-Xilinx Alveo boards featuring UltraScale+ FPGAs. Find out more in the OpenNIC repository
This framework is ideal to scale out your application without CPU intervention. Note that UDP is lightweight but no reliable. AUP provides example designs with UDP support at 100 Gbps in Vitis, this repository is also tightly coupled with the PYNQ project and provides support for distributed Alveo configuration on top of Dask. Find out more in the VNx repository
Floorplanning and pipelining tool for Vivado HLS dataflow designs. AutoBridge repository
Polyhedral-Based Systolic Array Auto-Compilation. AutoSA repository
A floorplan-integrated extension to high-level synthesis (HLS) C++ for task-parallel programs. TAPA repository
Parallel Physical Implementation of FPGA HLS Designs. RapidStream repository
Analysis and Optimization of the Implicit Broadcasts in FPGA HLS to Improve Maximum Frequency. Vivado-hls-broadcast-optimization repository
Stencil with Optimized Dataflow Architecture Compiler. Soda Compiler repository
Accelerating SSSP for power-law graphs using an FPGA. SPLAG respository
Enabling Software Programmers to Design Efficient FPGA Accelerators. AutoDSE repository
An FPGA accelerator for general-purpose Sparse-Matrix Dense-Matrix Multiplication (SpMM). SpMM repository
Reconfigurable Heterogeneous Architecture Framework aiming to provide operating system abstractions. Coyote repository
Data-Centric Parallel Programming compiles code in various programming languages and paradigms (Python/Numpy, MATLAB, TensorFlow) and maps it efficiently to CPUs, GPUs, and FPGAs with high utilization, on par with the state-of-the-art. Find out more in the DaCe repository
Allows easy kernel development and integration with various popular Big Data analytics frameworks based on Apache Arrow. Fletcher will generate all the interfaces and provide the kernel designer with simple and easy to understand interface corresponding to the data types of their application. This raises the abstraction to records and tables instead of buffers and bytes. Fletcher has platform support for Alveo
A tool that enables Fortran in the AMD Vitis ecosystem by adapting the LLVM IR to be compliant with the requirements of the Vitis backend. It adds support to the HLS constructs in Fortran. Legacy Fortran codes can now be run on FPGA and optimised directly in the native language without the costly manual conversion to C++. Fortran-HLS repository
A collection of extensions for Vitis to improve developer quality of life, including CMake integration, better vectorization support, support for simulating dataflow kernels with feedback dependencies. hlslib repository
HLS-based Graph Processing Framework on FPGAs. ThunderGP repository
ScaleHLS is a next-generation HLS compilation flow, on top of a multi-level compiler infrastructure called MLIR. ScaleHLS repository
An Algorithm-Centric FPGA Programming and Synthesis Flow. PyLog repository
Fully integrated framework that allows to speedup your C/C++, Python, Java and Scala applications with zero code changes. InAccel Coral is a framework that allows the distributed acceleration of large data sets across clusters of FPGA resources using simple programming models. The InAccel framework is available by default on the ETH HACC. Find out more InAccel.
Universities can also access to InAccel technology InAccel University
OctoRay is a Python framework which allows the user to easily scale up any FPGA application to multiple FPGAs using Dask. It supports at the moment all FPGA boards that are supported by PYNQ, so all PYNQ boards and Alveo cards. OctoRay repository
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