Additional Material

Learning Path

Versal Adaptive SoC Design Process Hubs
- Using this interactive page, you can select the area you are interested in, then using the flow chart you can find related documentation
AIE and AIE-ML Architecture, AM009 and AM020
- AIE Tile, interfaces
- Data Movement
- Scalar and Vector processors
- Vector and Accumulator registers
AIE Tool Flow UG1076
- Compile and simulation of an AIE Graph
- Performance Analysis
- Program PS/Host Application
- Integrate Application using Vitis Tool flow
- Debugging the AIE application
AIE Kernel and Graph Programming UG1079
- Programming
  - Scalar and Vector
  - Single Kernel
  - Graph
- AIE API / intrinsics
- Window and Stream Data API
ACAP System and Solution Planning UG1504
- Application Partition
- Memory and Data movement
- Custom Data flow /Precisions
- Compute intensive Tasks
Hardware, IP, and Platform Development Methodology UG1387
- Key IP: the Control, Interface, and Processing System (CIPS) IP
- Planning Considerations
  - Traditional Design Flow
  - Platform-Based Design Flow
  - Dynamic Function eXchange