Post-Link Recompile of an AI Engine Application

Version: Vitis 2022.1


AI Engine application development can start early in the system development stage. Little by little, the AI Engine development team and the hardware development team converge to an interface between the Adaptable Engine and the AI Engine array. At some point, this interface is fixed and should not be changed. This tutorial shows you how to modify an AI Engine application after the platform has been frozen while avoiding a complete Vivado® tool run, which can take a long time if timing closure requires specific attention.

There are two ways to perform this operation:

  1. Recompile the AI Engine application right after the link stage, using specific constraints to set the interface ports.

  2. Create an intermediate platform which embeds these constraints.

In the first case, you have to extract the constraints from the files generated by the AI Engine compiler and use them as input constraints when you run it for the second time.

In the second case, running the AI Engine tools provides a fixed platform that acts as a constraint on the AI Engine array – Adaptable Engine interface specification. This tutorial explains the complete flow for these two cases.

This tutorial details all the steps to perform hardware emulation (hw_emu), but it supports also the hardware implementation flow by changing the compilation target.

Before You Begin

This tutorial requires a number of tools and files to be installed:

  • Download and install the Vitis™ software platform from here. See the installation instructions here.

  • Download and install the Vitis Embedded Base Platform VCK190.

  • Download and install the common image for embedded Vitis platforms for Versal® ACAP.

The AI Engine development documentation is also available here.

Before starting this tutorial, run the following steps:

  1. Set up your platform by running the xilinx-versal-common-v2022.1/environment-setup-cortexa72-cortexa53-xilinx-linux script as provided in the platform download. This script sets up the SYSROOT and CXX variables. If the script is not present, you must run the xilinx-versal-common-v2022.1/

  2. Set up your ROOTFS to point to xilinx-versal-common-v2022.1/rootfs.ext4.

  3. Set up your IMAGE to point to xilinx-versal-common-v2022.1/Image.

  4. Set up your PLATFORM_REPO_PATHS environment variable based on where you downloaded the platform.

Accessing the Tutorial Reference Files

  1. To access the reference files, type the following into a terminal: git clone

  2. Navigate to the PostLinkRecompile directory.

The sub-directory Files contains all the source files necessary for this tutorial.

An script is provided to initialize the platform name.

AI Engine Application Post-Link Recompile

This tutorial contains the following labs:

  • Lab 1 is based on a direct recompile Makefile.

  • Lab 2 is based on a Vitis Makefile.

  • Lab 3 is based on the Vitis IDE flow.

Each lab is divided into the following phases:

  1. Creating an AI Engine application using the VCK190 platform with all necessary PL kernels added, and linking the complete system.

  2. Creating a new AI Engine application with interface location constraints (Lab 1) or with the previously created fixed platform (Labs 2 and 3), adding a PS application, and running hardware emulation.


This tutorial shows you how to modify an AI Engine application after the platform has been frozen. It demonstrates a Vitis IDE flow and a Makefile flow.

Completing this tutorial should give you confidence to develop AI Engine designs based on a hardware/software platform, knowing that you can modify the AI Engine part and the processing system control application. The only limitation is that the hardware connection between the AI Engine array and the programmable logic (PL) must be kept fixed.


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