P2P bandwidth Example

This is simple example to test Synchronous and Asyncronous data transfer between SSD and FPGA.

KEY CONCEPTS: P2P, SmartSSD, XDMA

KEYWORDS: XCL_MEM_EXT_P2P_BUFFER, pread, pwrite

PCIe peer-to-peer communication (P2P) is a PCIe feature which enables two PCIe devices to directly transfer data between each other without using host RAM as a temporary storage. The latest version of SDx PCIe platforms support P2P feature via PCIe Resizeable BAR Capability

In this Example we highlight the Synchronous and Asynchronous data transfer between SSD and FPGA and capture the performance numbers for p2p transfer, Kernel and XDMA.

Following is the real log reported while running the design on samsung platform:

./host copy_kernel.xclbin -w /dev/nvme0n1
INFO: Successfully opened NVME SSD /dev/nvme0n1
INFO: Preparing 1048576KB test data in 8 pipelines
############################################################
                     Synchronous P2P
############################################################
INFO: Kick off test
HOST -> FPGA(host BO) -> FPGA(p2p BO) -> SSD
 overall      556211ms    100.00%    1841.03MB/s
     p2p      359223ms     64.58%    2850.60MB/s
  kernel      199578ms     35.88%    5130.83MB/s
    XDMA      313203ms     56.31%    3269.45MB/s
INFO: Evaluating test result
INFO: Test passed

EXCLUDED PLATFORMS

Platforms containing following strings in their names are not supported for this example :

zc
u200
u250
u50
u280
aws

DESIGN FILES

Application code is located in the src directory. Accelerator binary files will be compiled to the xclbin directory. The xclbin directory is required by the Makefile and its contents will be filled during compilation. A listing of all the files in this example is shown below

src/copy_kernel.cpp
src/host.cpp

COMMAND LINE ARGUMENTS

Once the environment has been configured, the application can be executed by

./host <copy_kernel XCLBIN> -r /dev/nvme0n1