Stream Kernel to Kernel (RTL Kernel)¶
This is a simple Vector Increment RTL Kernel to Kernel design with 1 Stream input and 1 Stream output that demonstrates on how to process an input stream of data for computation in an application.
KEY CONCEPTS: Read/Write Stream, Create/Release Stream, RTL Kernel
KEYWORDS: cl_stream, CL_STREAM_EOT
This example demonstrates the use of RTL kernels for addition with
stream interfaces. Two kernels, my_adder1
and myadder2
are
connected by a stream interface. Each kernel simply increments the input
by 1 and returns the result. Kernel to kernel stream interfaces need to
be specified in the kernel linking stage via a .ini
file in the
following manner.
stream_connect=myadder1_1.out:myadder2_1.in
RTL kernels can be integrated to Vitis using RTL Kernel Wizard
.
These kernels have the same software interface model as OpenCL and C/C++
kernels. That is, they are seen by the host application as functions
with a void return value, scalar arguments, and pointer arguments.
The RTL Kernel Wizard automates some of the steps that need to be taken
to ensure that the RTL IP is packaged into a kernel that can be
integrated into a system in Vitis environment. A kernel.xml
file is
generated to match the software function prototype and behavior
specified in the wizard.
EXCLUDED PLATFORMS¶
Platforms containing following strings in their names are not supported for this example :
zc
xdma
xilinx_u250_qep
aws
samsung
DESIGN FILES¶
Application code is located in the src directory. Accelerator binary files will be compiled to the xclbin directory. The xclbin directory is required by the Makefile and its contents will be filled during compilation. A listing of all the files in this example is shown below
src/gen_xo_myadder1.tcl
src/gen_xo_myadder2.tcl
src/host.cpp
COMMAND LINE ARGUMENTS¶
Once the environment has been configured, the application can be executed by
./vadd_stream <myadder XCLBIN>