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Vitis Accel Examples
2021.2

Table of Contents

  • Prerequisites
  • Supported Shells
  • Compilation and Execution

Category of Examples

  • Hello World
  • AIE Examples
  • Host OpenCL
  • Host Native XRT
  • Host Python
  • C++ Kernels
    • Array Partition
    • Burst Read/Write
    • BIND OP and STORAGE
    • Critical Path
    • Custom Data Type
    • Dataflow Using HLS Stream
    • Dataflow Using Array of HLS Stream
    • Loop Dependency Inter
    • Global Memory Two Banks
    • Stream Chain Matrix Multiplication
    • Local Memory Two Parallel Read/Write
    • Loop Pipelining
    • Loop Reordering
    • Array Block and Cyclic Partitioning
    • Port Width Widening
    • PLRAM Memory Access
    • Vector Addition
    • Shift Register
    • Systolic Array
    • Wide Memory Read/Write
  • Demos
  • Emulation Examples
  • Performance Examples
  • System Optimization Kernels
  • RTL Kernels
  • OpenCL Kernels
  • Validate

Common Utilities

  • Common Files

Versions

  • Master (2021.2)
  • Previous Versions

This Page

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Vitis Accel Examples
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  • C++ Kernels
  • View page source

C++ KernelsΒΆ

This page contains examples for users who are new to Xilinx Vitis OpenCL Flows. The focus of the examples is towards code optimization using HLS C/C++ kernels for Xilinx devices.

List of Examples

  • Array Partition
  • Burst Read/Write
  • BIND OP and STORAGE
  • Critical Path
  • Custom Data Type
  • Dataflow Using HLS Stream
  • Dataflow Using Array of HLS Stream
  • Loop Dependency Inter
  • Global Memory Two Banks
  • Stream Chain Matrix Multiplication
  • Local Memory Two Parallel Read/Write
  • Loop Pipelining
  • Loop Reordering
  • Array Block and Cyclic Partitioning
  • Port Width Widening
  • PLRAM Memory Access
  • Vector Addition
  • Shift Register
  • Systolic Array
  • Wide Memory Read/Write
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