Design Flows

The common tool and library pre-requisites that apply across all design flows are documented in the requirements section above.

Recommended design flows are described as follows:

Shell Environment

Setup the build environment using the Vitis and XRT scripts.

source /opt/xilinx/Vitis/2020.2/
source /opt/xilinx/xrt/
export PLATFORM_REPO_PATHS=/opt/xilinx/platforms

For csh users, please look for corresponding scripts with .csh suffix and adjust the variable setting command accordingly.

Setting PLATFORM_REPO_PATHS to the installation folder of platform files can enable makefiles in this library to use DEVICE variable as a pattern. Otherwise, full path to .xpfm file needs to be provided via DEVICE variable.

HLS Cases Command Line Flow

cd L1/tests/hls_case_folder


Test control variables are:

  • CSIM for high level simulation.
  • CSYNTH for high level synthesis to RTL.
  • COSIM for co-simulation between software test bench and generated RTL.
  • VIVADO_SYN for synthesis by Vivado.
  • VIVADO_IMPL for implementation by Vivado.

For all these variables, setting to 1 indicates execution while 0 for skipping. The default value of all these control variables are 0, so they can be omitted from command line if the corresponding step is not wanted.

Vitis Cases Command Line Flow

cd L2/tests/vitis_case_folder

# build and run one of the following using U280 platform
make run TARGET=sw_emu DEVICE=/path/to/xilinx_u280_xdma_201920_3.xpfm

# delete generated files
make cleanall

Here, TARGET decides the FPGA binary type

  • sw_emu is for software emulation
  • hw_emu is for hardware emulation
  • hw is for deployment on physical card. (Compilation to hardware binary often takes hours.)

Besides run, the Vitis case makefile also allows host and xclbin as build target.